Core8051-M Actel, Core8051-M Datasheet - Page 59

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Core8051-M

Manufacturer Part Number
Core8051-M
Description
Microcontroller Modules & Accessories 8B Microcontroller
Manufacturer
Actel
Datasheet

Specifications of Core8051-M

Product
Microcontroller Modules
Data Bus Width
8 bit, 16 bit, 32 bit
Clock Speed
36 MHz
Interface Type
JTAG
7 – List of Changes
List of Changes
Date
August 2010
The following table lists critical changes that were made in each revision of the handbook
The core version was updated to v2.4
Type was changed from input to output for the MEMDATAO signal in
Core8051s
The
behavior of the processor is undefined when attempting to execute a MUL, DIV or
DA instruction while the processor is not configured to include support for these
instructions.
The name of the Interrupt Enable register was changed from IEN to IE in
Core8051s SFR
"Interrupts"
The
register implements a subset of the Timer Control (TCON) register.
In
was corrected. It had previously been listed as "ASH." The
corrected from "BSH."
A footnote was added to the table stating that the A5H opcode is used as a trap
instruction for the implementation of software breakpoints.
The
Small Device C Compiler (SDCC) is bundled with Actel's SoftConsole software
development environment.
Table 5-8 • Core8051s Instruction Set in Hexadecimal
"Interrupt Control Register (icon)" section
"C Compiler Support" section
"Optional Registers and Instructions" section
Ports.
section.
Registers, the
R e v i s i o n 2
"Interrupt Enable Register (ie)"
was modified by adding the statement that the
Changes
was revised to state that the ICON
was updated to state that the
Order, the opcode
"B5H"
section, and the
opcode was
Table 2-1 •
Table 4-1 •
"A5H*"
31, 33,
41,
Page
N/A
18
22
34
33
46
43
59

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