Core8051-M Actel, Core8051-M Datasheet - Page 51

• Manufacturer Part Number: Core8051-M
• Description: Microcontroller Modules & Accessories 8B Microcontroller
• Manufacturer: Actel

Specifications of Core8051-M

• Product: Microcontroller Modules
• Data Bus Width: 8 bit, 16 bit, 32 bit
• Clock Speed: 36 MHz
• Interface Type: JTAG

6 – Instruction Timing
Program Memory Bus Cycle
Figure 6-1 • Program Memory Fetch Cycle Without Wait States
mempsack
memdatao
mempswr
memaddr
mempsrd
memdatai
memwr
memrd
clk
The execution for instruction N is performed during the fetch of instruction N + 1. A program memory
fetch cycle without wait states is shown in
shown in
on page
through to
conventions are used in
Table 6-1 • Conventions Used in Figure 18 to Figure 31
Convention
Tclk
N
(N)
N+1
Addr
Data
read sample
write sample
ramcs
0 ns
52. A program memory read cycle with wait states is shown in
Figure 6-2 on page
Figure 6-12 on page 57
50 ns
N
Time period of clk signal
Address of actually executed instruction
Instruction fetched from address N
Address of next instruction
Address of memory cell
Data read from address Addrl
Point of reading the data from the bus into the internal register
Point of writing the data from the bus into memory
Off-core signal is made on the base ramwe and clk signals
(N)
Figure 6-1
Read
Sample
Sample
52. A program memory read cycle without wait states is shown in
N + 1
(N + 1)
100 ns
to
have been taken from the
Figure 6-14 on page
Sample
Read
Sample
R e v i s i o n 2
N + 2
Figure
(N + 2)
150 ns
6-1. A program memory fetch cycle with wait states is
Sample
Read
Sample
Description
57.
200 ns
Core8051
Figure 6-4 on page
Datasheet. The following
250 ns
53.
Figure 6-3
Figure 6-1
300 ns
51