Core8051-M Actel, Core8051-M Datasheet - Page 6

• Manufacturer Part Number: Core8051-M
• Description: Microcontroller Modules & Accessories 8B Microcontroller
• Manufacturer: Actel

Specifications of Core8051-M

• Product: Microcontroller Modules
• Data Bus Width: 8 bit, 16 bit, 32 bit
• Clock Speed: 36 MHz
• Interface Type: JTAG

Introduction
Utilization and Performance
6
Table 1
of Core8051s for each type of FPGA technology. These tables do not cover every possible configuration,
but instead list a range of configurations which should give a good indication of the expected resource
usage and performance of the core. Abbreviated versions of configuration options are used in the tables
to aid readability. The meanings of the entries in the debug, program memory access control, data
memory access control, and internal RAM columns are described in the following paragraphs.
Debug Column
Program Memory Access Control
Data Memory Access Control
Internal RAM
•
•
•
•
•
•
•
•
•
None: Debug logic is not included.
I/Os: Debug logic is included and general purpose I/Os are used for the debug connection.
UJTAG: Debug logic is included and the dedicated JTAG pins of the device and the UJTAG macro
are used for the debug connection.
ACK: Acknowledge signal (MEMPSACKI) is used to control access to program memory.
X: X (where X can range from 0 to 7) wait states are inserted in each access to program memory,
instead of using acknowledge control.
ACK: Acknowledge signal (MEMACKI) is used to control accesses to data memory.
X: X (where X can range from 0 to 7) wait states are inserted in each access to data memory,
instead of using acknowledge control.
Instantiated: Internal 256x8 RAM is implemented using an instantiated RAM block.
Inferred: Internal 256x8 RAM is implemented by inferring RAM during synthesis.
through
Table 7 on page 13
give resource usage and performance data for various configurations
R e vi s i o n 2