Core8051-M Actel, Core8051-M Datasheet - Page 35

• Manufacturer Part Number: Core8051-M
• Description: Microcontroller Modules & Accessories 8B Microcontroller
• Manufacturer: Actel

Specifications of Core8051-M

• Product: Microcontroller Modules
• Data Bus Width: 8 bit, 16 bit, 32 bit
• Clock Speed: 36 MHz
• Interface Type: JTAG

5 – Instruction Set
The Core8051s instructions are binary code compatible and perform the same functions as the industry-
standard 8051. This is the ASM51 instruction set. Some of these instructions, however, are not enabled
by default and so must be explicitly enabled if required.
Table 5-1
Table 5-3 on page 36
Table 5-8 on page
more detailed information about the Core8051s instruction set, refer to the
Details User’s
Table 5-1 • Notes on Data Addressing Modes
Table 5-2 • Notes on Programming Addressing Modes
Rn
direct
@Ri
#data
#data 16
bit
A
addr16
addr11
Rel
and
Guide.
Table 5-2
Destination address for LCALL and LJMP may be anywhere within the 64 kbytes
program memory address space.
Destination address for ACALL and AJMP will be within the same 2 kbytes page of
program memory as the first byte of the following instruction.
SJMP and all conditional jumps include an 8-bit offset byte. Range is from plus 127 to
minus 128 bytes, relative to the first byte of the following instruction.
Working register, R0–R7
128 internal RAM locations, any I/O port, control or status register
Indirect internal or external RAM location addressed by register, R0 or R1
8-bit constant included in instruction
16-bit constant included as bytes 2 and 3 of instruction
128 software flags, any bit-addressable I/O pin, control or status bit
Accumulator
41, the instructions are ordered in the hexadecimal order of the operation code. For
through
contain notes for mnemonics used in the various instruction set tables. In
Table 5-7 on page
R e v i s i o n 2
40, the instructions are ordered in functional groups. In
Core8051 Instruction Set
35