Core8051-M Actel, Core8051-M Datasheet - Page 30

• Manufacturer Part Number: Core8051-M
• Description: Microcontroller Modules & Accessories 8B Microcontroller
• Manufacturer: Actel

Specifications of Core8051-M

• Product: Microcontroller Modules
• Data Bus Width: 8 bit, 16 bit, 32 bit
• Clock Speed: 36 MHz
• Interface Type: JTAG

Core8051s Features
External Data Memory Space
Core8051s can address up to 64 kbytes of external data memory space, from 0000H to FFFFH. This
memory is external to the core, not necessarily to the FPGA. In the Core8051s, the upper 4 kbytes
(F000H to FFFFH) of external data memory space is mapped to an APB bus. The lower 60 kbytes is
mapped to the external memory bus interface.
External Data Interface
The external memory bus interface
(Table 2-1 on page
18) services data memory when the MEMRD
signal is active. Core8051s writes into external data memory when the CPU executes MOVX @Ri,A or
MOVX @DPTR,A instructions. The external data memory is read when the CPU executes MOVX A,@Ri
or MOVX A,@DPTR instructions. There is improved variable length of the MOVX instructions to access
fast or slow external RAM and external peripherals. The external data memory can use variable length
accesses (MEMACKI-controlled), or a fixed number of stretch cycles may be inserted on each read or
write. Refer to
"External Data Memory Access" on page 23
for more information about configuring
access to external data memory.
APB Interface
Core8051s based systems use an APB bus for connecting peripherals, where the Core8051s acts as the
bus master. The width of the APB bus on Core8051s can be selected to match the width of the widest
APB peripheral in the system (8, 16, or 32 bits). As the Core8051s is an 8-bit processor and it is not
possible to indicate transaction size on the APB, reads and writes from or to the APB bus in 16-bit or 32-
bit mode are accomplished by means of newly defined SFRs, hereafter referred to as X registers. For
example, to perform a write to a 32-bit APB peripheral, the program running on the Core8051s must first
perform three individual 8-bit writes to X registers (XWB1, XWB2, and XWB3). These registers hold the
value to be written out on PWDATA [31:8]. When the program subsequently does a write to the APB
address in question, the 8 bits of the write data associated with that write cycle are put out on the
PWDATA [7:0] and the three write “X registers” are put onto the APB bus as PWDATA [31:8].
16-bit and 32-bit reads from the APB are handled in a similar manner. To perform a 32-bit read from an
APB location, the program must perform a read of the APB location, from which it immediately obtains
bits [7:0] of the 16 or 32 bits on PRDATA[7:0]. Subsequently, the program must read the three read X
registers (XRB1, XRB2, and XRB3) to get bits [31:8], which were read from the APB peripheral and
latched in these SFRs at the time of the APB transaction.
For the 4 kbytes of memory space allocated to the APB interface, only word access is possible, where
word refers to an 8-bit, 16-bit, or 32-bit entity, for their respective APB bus implementations.
The APB interface of Core8051s will typically be connected to CoreAPB3, which can in turn connect to
up to 16 peripherals such as CoreTimer and CoreGPIO. Often the programmer accessible registers in
these peripherals will be located at 32-bit word boundaries in the address map. This means that
consecutive registers are located at address offsets 0x00, 0x04, 0x08, 0x0C, and so on. Core8051s must
take account of this when accessing such peripherals. For example, to access successive register
locations in a peripheral attached to slave slot 0 on CoreAPB3, Core8051s would issue addresses
0xF000, 0xF004, 0xF008, 0xF00C, and so on.
The net effect is that only every fourth location in the APB space is usable if the peripherals are designed
such that their registers are located at 32-bit word boundaries in the memory map. If all of the 4 kbytes of
APB space connects to peripherals of this type, then there are only 1,024 separately addressable
locations, which equates to 64 locations per peripheral, assuming CoreAPB3 is used.
Note that the APB data width is independent of the addressing scheme. Each location can hold a value
which is 8, 16, or 32 bits wide. The APB data width configurable option of Core8051s should be set to
match the largest data width to be accessed on the APB interface.
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