LS-E2-L-BASE-PC-N Lattice, LS-E2-L-BASE-PC-N Datasheet - Page 14

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LS-E2-L-BASE-PC-N

Manufacturer Part Number
LS-E2-L-BASE-PC-N
Description
MCU, MPU & DSP Development Tools ispLEVER Base - LS ECP2 50E Std Dev Kit
Manufacturer
Lattice
Datasheet

Specifications of LS-E2-L-BASE-PC-N

Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lattice Semiconductor
Table 28. PCI Connections - Component Side
J14
10
11
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
1
2
3
4
5
6
7
8
9
-12V
PCI_TCK
GND
PCI_TDO
+5V
+5V
PCI_INTB_N
PCI_INTD_N
PCI_PRSNT1_N
PCIX_ECC4
PCI_PRSNT2_N
PCIX_ECC2
GND
PCI_CLK
GND
PCI_REQ_N
+3.3V
PCI_AD31
PCI_AD29
GND
PCI_AD27
PCI_AD25
3.3V
PCI_CBE3_N
PCI_AD23
GND
PCI_AD21
PCI_AD19
3.3V
PCI_AD17
PCI_CBE2_N
GND
PCI_IRDY_N
+3.3V
PCI_DEVSEL_N
PCIXCAP
LOCK#
PCI_PERR_N
+3.3V
PCI_SERR_N
+3.3V
PCI_CBE1_N
PCI_AD14
GND
Signal Name
LatticeECP2 Pin
AA10
AB2
AA3
AB3
AB4
AA5
AB5
AA6
AB6
AB7
AA7
AB8
AA8
AA9
AB9
U11
J14
W3
R1
14
Y2
Y3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LatticeECP2 Standard Evaluation Board
sysIO Bank
5
5
6
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Decoupling cap
TP16, PD if master
TP17, J3, J13
NC
NC
J19
J19
J23
D20, J22
TP15
User’s Guide
Notes

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