LS-E2-L-BASE-PC-N Lattice, LS-E2-L-BASE-PC-N Datasheet - Page 18

• Manufacturer Part Number: LS-E2-L-BASE-PC-N
• Description: MCU, MPU & DSP Development Tools ispLEVER Base - LS ECP2 50E Std Dev Kit
• Manufacturer: Lattice

Specifications of LS-E2-L-BASE-PC-N

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
High-Speed Differential
The board supports testing of up to eight differential pairs using two types of connectors, SMA and RJ45. Each pair
has provision for a “line-to-line” resistor as well as single-ended series resistors (for maximum flexibility these resis-
tors are not included with the board). The resistors can be used as termination or in combination to provide signal
emulation (level shifting). For more information on signal emulation and signal types, please refer to Lattice techni-
cal note number TN1102, LatticeECP2 sysIO Usage Guide, available on the Lattice web site at www.lattices-
emi.com.
Table 37. Differential SI Connectors
Test Points
For GPIO (general purpose I/O) testing or monitoring, numerous test points are provided. The test points are
labeled according to the associated I/O pin location, for example TP_A21. These test points have been arranged in
grids that have grounds and V
end of this document for more information.
Note that the test points for J21 and N21 have locations for zero ohm resistors (R115 and R117) to allow isolation
of the test points from the oscillator clock. By default these resistors are not installed on the board.
Switches
Switch 1 (SW1) on the top edge of the board is an eight-switch block that is part of the prototyping area. A switch in
the down position produces a low (logic 0), while the up position produces a high (logic 1). All SW1 signals go to
bank 1.
1. All support true LVDS.
2. The shorting trace must be cut before installing the resistor.
3. R27 must be installed and J22 must be open if using J21.
Location
U6-8
U6-1
U6-2
U6-3
U6-4
U6-5
U6-6
U6-7
J27
J28
J26
J25
J21
J20
J15
J16
Connector
Type
RJ45
RJ45
RJ45
RJ45
SMA
SMA
SMA
SMA
CCIO
s placed nearby to allow for easy prototyping. Please refer the schematics at the
Pin
M5
M6
P1
P2
R1
R2
R3
E2
E1
K3
K4
L3
T4
L4
J2
J1
LatticeECP2
18
GPLLC FB
GDLLC IN
PCLKC IN
GPLLC IN
GPLLT FB
PCLKT IN
GDLLT IN
GPLLT IN
LatticeECP2 Standard Evaluation Board
Type
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
1
Series
R87
R24
R25
R84
R85
R28
R29
R89
R90
R14
R15
R16
R17
R77
R78
R79
2
Resistors
User’s Guide
Line-to-Line
R30
R26
R86
R91
R18
R19
R80
R81
3