LS-E2-L-BASE-PC-N Lattice, LS-E2-L-BASE-PC-N Datasheet - Page 5

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LS-E2-L-BASE-PC-N

Manufacturer Part Number
LS-E2-L-BASE-PC-N
Description
MCU, MPU & DSP Development Tools ispLEVER Base - LS ECP2 50E Std Dev Kit
Manufacturer
Lattice
Datasheet

Specifications of LS-E2-L-BASE-PC-N

Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lattice Semiconductor
Table 3. sysCONFIG Header Pinout (J40)
Table 4. sysCONFIG Loop-Through Header Pinout (J41)
JTAG and sysCONFIG Jumpers
There are several JTAG and sysCONFIG cabling options that can be selected using jumpers.
CCLK
BUSY / SISPI
DI/D0
D7 / DOUT
DONE
D7
D6
D5
D4
D3
D2
D1
D0
CSN
CS1N
Vcc Bank8
Ground
1. See section below on jumpers.
CCLK
N/C
DOUT / CSSON
N/C
DONE
D7
D6
D5
D4
D3
D2
D1
D0
CSN / N/C
CS1N / N/C
N/C
Ground
1. See section below on jumpers.
1
Function
Function
1
1
1
1
1
11
13
15
17
19
21
23
25
27
29
31
33
11
13
15
17
19
21
23
25
27
29
31
33
1
3
5
7
9
1
3
5
7
9
Pin
Pin
5
10
12
14
16
18
20
22
24
26
28
30
32
34
10
12
14
16
18
20
22
24
26
28
30
32
34
LatticeECP2 Standard Evaluation Board
2
4
6
8
2
4
6
8
Ground
D6
Vcc Bank8
INITN
PROGRAMN
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
WRITEN
CFG0
CFG1
CFG2
Ground
N/C
N/C
INITN
PROGRAMN
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
WRITEN
N/C
N/C
N/C
Function
Function
User’s Guide

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