XC3S1600E-5FG320C Xilinx Inc, XC3S1600E-5FG320C Datasheet - Page 18

• Manufacturer Part Number: XC3S1600E-5FG320C
• Description: PROGRAMMABLE MICROCHIP
• Manufacturer: Xilinx Inc

I/O Banking Rules
When assigning I/Os to banks, these V
followed:
1. All V
2. All V
3. The V
4. If a bank does not have any V
If any of the standards assigned to the Inputs of the bank
use V
observed:
1. All V
2. All V
3. The V
If V
all associated V
user I/Os or input pins.
Package Footprint Compatibility
Sometimes, applications outgrow the logic capacity of a
specific Spartan-3E FPGA. Fortunately, the Spartan-3E
family is designed so that multiple part types are available in
pin-compatible package footprints, as described in
4. In some cases, there are subtle differences between
devices available in the same footprint. These differences
DS312-2 (v1.1) March 21, 2005
Advance Product Specification
REF
bank is unused.
the same voltage level.
I/Os of any given bank must agree. The Xilinx
development software checks for this.
Table 4
supply.
connect V
3.3V. Some configuration modes might place additional
V
for more information.
the same voltage level.
Inputs of the bank must agree. The Xilinx development
software checks for this.
standards use the V
CCO
REF
Figure 10: Spartan-3E I/O Banks (top view)
is not required to bias the input switching thresholds,
CCO
CCO
REF
REF
, then the following additional rules must be
CCO
REF
requirements. Refer to
describe how different standards use the V
R
pins must be connected within a bank.
lines associated with the bank must be set to
pins on the FPGA must be connected even if a
lines associated within a bank must be set to
CCO
levels used by all standards assigned to the
levels used by all standards assigned to the
REF
to an available voltage, such as 2.5V or
pins within the bank can be used as
REF
Bank 0
Bank 2
Table 3
supply.
DS312-2_26_021205
Configuration, page 56
CCO
describes how different
requirements,
CCO
Table 3
rules must be
and
Module
www.xilinx.com
CCO
are outlined for each package, such as pins that are uncon-
nected on one device but connected on another in the same
package or pins that are dedicated inputs on one package
but full I/O on another. When designing the printed circuit
board (PCB), plan for potential future upgrades and pack-
age migration.
The Spartan-3E family is not pin-compatible with any previ-
ous Xilinx FPGA family.
Dedicated Inputs
Dedicated Inputs are IOBs used only as inputs. Pin names
designate a Dedicated Input if the name starts with IP , for
example, IP or IP_Lxxx_x. Dedicated inputs retain the full
functionality of the IOB for input functions with a single
exception for differential inputs (IP_Lxxx_x). For the differ-
ential Dedicated Inputs, the on-chip differential termination
is not available. To replace the on-chip differential termina-
tion, choose a differential pair that supports outputs
(IO_Lxxx_x) or use an external 100Ω termination resistor on
the board.
ESD Protection
Clamp diodes protect all device pads against damage from
Electro-Static Discharge (ESD) as well as excessive voltage
transients. Each I/O has two clamp diodes: one diode
extends P-to-N from the pad to V
extends N-to-P from the pad to GND. During operation,
these diodes are normally biased in the off state. These
clamp diodes are always connected to the pad, regardless
of the signal standard selected. The presence of diodes lim-
its the ability of Spartan-3E I/Os to tolerate high signal volt-
ages. The V
Module 3
Supply Voltages for the IOBs
The IOBs are powered by three supplies:
1. The V
2. V
3. V
The I/Os During Power-On, Configuration, and
User Mode
All I/Os have ESD clamp diodes to their respective V
supply and from GND, as shown in
(1.2V), V
any order. Before the FPGA can start its configuration pro-
cess, V
reached their respective minimum recommended operating
banks, power the output drivers. The voltage on the
V
signal.
logic.
optimize the performance of various FPGA functions
such as I/O switching.
CCO
CCINT
CCAUX
CCINT
CCAUX
specifies the voltage range that I/Os can tolerate.
CCO
pins determines the voltage swing of the output
is the main power supply for the FPGA’s internal
is an auxiliary source of power, primarily to
IN
, V
supplies, one for each of the FPGA’s I/O
(2.5V), and V
absolute maximum rating in Table 1 of
CCO
Bank 2, and V
CCO
supplies can be applied in
CCO
Functional Description
Figure
and a second diode
CCAUX
1. The V
must have
CCINT
CCO
11