XC3S1600E-5FG320C Xilinx Inc, XC3S1600E-5FG320C Datasheet - Page 93

• Manufacturer Part Number: XC3S1600E-5FG320C
• Description: PROGRAMMABLE MICROCHIP
• Manufacturer: Xilinx Inc

Functional Description
JTAG Mode
The Spartan-3E FPGA has a dedicated four-wire IEEE
1149.1/1532 JTAG port that is always available any time the
FPGA is powered and regardless of the mode pin settings.
However, when the FPGA mode pins are set for JTAG mode
(M[2:0] = <1:0:1>), the FPGA waits to be configured via the
JTAG port after a power-on event or when PROG_B is
asserted. Selecting the JTAG mode simply disables the
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•
•
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Internal memory
Disk drive
Over network
Over RF link
Configuration
Memory
Source
Download Host
Intelligent
•
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•
Microcontroller
Processor
Tester
Computer
SERIAL_OUT
Recommend
open-drain
PROG_B
driver
VCC
GND
PROG_B
V
CLOCK
INIT_B
TMS
TCK
TDO
DONE
TDI
+2.5V
JTAG
Figure 61: Daisy-Chaining using Slave Serial Mode
Slave
Serial
Mode
P
‘1’
‘1’
‘1’
HSWAP
M2
M1
M0
CCLK
DIN
TDI
TMS
TCK
PROG_B
Spartan-3E
VCCINT
FPGA
+1.2V
GND
VCCAUX
VCCO_0
VCCO_2
www.xilinx.com
INIT_B
DONE
DOUT
TDO
VCCO_0
+2.5V
V
other configuration modes. No other pins are required as
part of the configuration interface.
Figure 62
The JTAG interface is easily cascaded to any number of
FPGAs by connecting the TDO output of one device to the
TDI input of the next device in the chain. The TDO output of
the last device in the chain loops back to the port connector.
V
+2.5V
illustrates a JTAG-only configuration interface.
Slave
Serial
Mode
P
‘1’
‘1’
‘1’
HSWAP
M2
M1
M0
CCLK
DIN
TDI
PROG_B
TMS
TCK
Spartan-3E
VCCINT
+1.2V
FPGA
GND
Advance Product Specification
DS312-2 (v1.1) March 21, 2005
VCCAUX
VCCO_0
VCCO_2
INIT_B
DOUT
DONE
TDO
VCCO_0
VCCO_2
+2.5V
DS312-2_55_022305
CCLK
DOUT
PROG_B
DONE
INIT_B
TMS
TCK
R