XC3S1600E-5FG320C Xilinx Inc, XC3S1600E-5FG320C Datasheet - Page 27

• Manufacturer Part Number: XC3S1600E-5FG320C
• Description: PROGRAMMABLE MICROCHIP
• Manufacturer: Xilinx Inc

Functional Description
The wide multiplexers can be used by the automatic tools or
instantiated in a design using a component such as the
F5MUX. The symbol, signals, and function are described
below. The description is similar for the F6MUX, F7MUX,
and F8MUX. Each has versions with a general output, local
output, or both.
Table 9: F5MUX Inputs and Outputs
20
I0
I1
S
LO
O
Signal
Figure 18: F5MUX with Local and General Outputs
Input selected when S is Low
Input selected when S is High
Select input
Local Output that connects to the F5 or FX CLB
pins, which use local feedback to the FXIN
inputs to the FiMUX for cascading
General Output that connects to the
general-purpose combinatorial or registered
outputs of the CLB
I0
I1
S
0
1
DS312-2_35_021205
Function
LO
O
www.xilinx.com
Table 10: F5MUX Function
For more details on using the multiplexers, see XAPP466:
"Using Dedicated Multiplexers in Spartan-3 FPGAs".
Carry and Arithmetic Logic
The carry chain, together with various dedicated arithmetic
logic gates, support fast and efficient implementations of
math operations. The carry logic is automatically used for
most arithmetic functions in a design. The gates and multi-
plexers of the carry and arithmetic logic can also be used for
general-purpose logic, including simple wide Boolean func-
tions.
The carry chain enters the slice as CIN and exits as COUT,
controlled by several multiplexers. The carry chain connects
directly from one CLB to the CLB above. The carry chain
can be initialized at any point from the BX (or BY) inputs.
The dedicated arithmetic logic includes the exclusive-OR
gates XORF and XORG (upper and lower portions of the
slice, respectively) as well as the AND gates GAND and
FAND (upper and lower portions, respectively). These gates
work in conjunction with the LUTs to implement efficient
arithmetic functions, including counters and multipliers, typ-
ically at two bits per slice. See
S
0
0
1
1
Inputs
I0
X
X
1
0
I1
X
X
1
0
Advance Product Specification
DS312-2 (v1.1) March 21, 2005
Figure 19
O
1
0
1
0
Outputs
and
Table
LO
11.
1
0
1
0
R