AD6634BBC Analog Devices Inc, AD6634BBC Datasheet - Page 35

• Manufacturer Part Number: AD6634BBC
• Description: IC,RF/Baseband Circuit,CMOS,BGA,196PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Series: AD6634r

Specifications of AD6634BBC

• Rohs Status: RoHS non-compliant
• Rf Type: Cellular, CDMA2000, EDGE, GPRS, GSM
• Number Of Mixers: 1
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 196-CSPBGA
• Current - Supply: -
• Frequency: -
• Gain: -
• Noise Figure: -
• Secondary Attributes: -

PxCH[1:0]
Master/Slave PCLK Modes
The parallel ports may operate in either Master or Slave mode.
The mode is set via the Port Clock Control register (address
0x1E). The parallel ports power up in Slave mode to avoid
possible contentions on the PCLK pin.
In Master mode, PCLK is an output whose frequency is the
AD6634 clock frequency divided by the PCLK divisor. Since
values for PCLK_divisor[2:1] can range from 0 to 3, integer
divisors of 1, 2, 4, or 8, respectively, can be obtained. Since the
maximum clock rate of the AD6634 is 80 MHz, the highest PLCK
rate in Master mode is also 80 MHz. Master mode is selected
by setting Bit 0 of address 0x1E.
In Slave mode, external circuitry provides the PCLK signal. Slave
mode PCLK signals may be either synchronous or asynchronous.
The maximum Slave mode PCLK frequency is 100 MHz.
Parallel Port Pin Functionality
The following describes the functionality of the pins used by the
parallel ports.
PCLK—Input/Output. As an output (Master mode), the maximum
frequency is CLK/N, where CLK is AD6634 clock and N is an
integer divisor from 1, 2, 4, or 8. As an input (Slave mode),
it may be asynchronous relative to the AD6634 CLK. This pin
powers up as an input to avoid possible contentions. Other port
outputs change on the rising edge of PCLK.
REQ—Active HIGH output, synchronous to PCLK. A logic
HIGH on this pin indicates that data is available to be shifted out
of the port. A logic HIGH value remains high until all pending
data has been shifted out.
ACK—Active HIGH asynchronous input. Applying a logic LOW
on this pin inhibits parallel port data shifting. Applying a logic
HIGH to this pin when REQ is high causes the parallel port to
shift out data according the programmed data mode. ACK is
sampled on the rising edge of PCLK. Assuming REQ is asserted,
the latency from the assertion of ACK to data appearing at the
parallel port output is no more than 1.5 PCLK cycles (see
Figure 12). ACK may be held high continuously; in this case,
when data becomes available, shifting begins 1 PCLK cycle after
the assertion of REQ (see Figure 36).
PAIQ, PBIQ—High whenever I data is present on the port output,
low otherwise.
REV. 0
Px[15:0]
PxACK
PxREQ
PCLK
PxlQ
Figure 39. AGC Output with RSSI Word
I[15:0]
t
t
t
t
DPREQ
DPP
DPIQ
DPCH
PxCH[0] = AGC#
PxCH[1] = 0
Q[15:0]
PxCH[0] = AGC#
PxCH[1] = 1
RSSI[11:0]
–35–
PACH[1:0], PBCH[1:0]—These pins serve to identify data in
both of the data modes. In Channel mode, these pins form a 2-bit
binary number identifying the source channel of the current
data-word. In AGC mode, [0] indicates the AGC source (0 = AGC
A, 1 = AGC B), and [1] indicates whether the current data-word
is I/Q data (0) or an RSSI word (1).
PA[15:0], PB[15:0]—Parallel Output Data Ports. Contents and
format are mode-dependent.
LINK PORT
The AD6634 has two configurable link ports that provide a
seamless data interface with the TigerSHARC DSP. Each link
port allows the AD6634 to write output data to the receive
DMA channel in the TigerSHARC for transfer to memory.
Since they operate independently of each other, each link port can
be connected to a different TigerSHARC or different link ports
on the same TigerSHARC. Figure 40 shows how to connect one of
the two AD6634 link ports to one of the four TigerSHARC link
ports. Link Port A is configured through register 0x1B and Link
Port B is configured through register 0x1D.
Link Port Data Format
Each link port can output data to the TigerSHARC in five different
formats: 2-channel, 4-channel, dedicated AGC, redundant AGC
with RSSI word, and redundant AGC without RSSI word. Each
format outputs two bytes of I data and two bytes of Q data to form a
4-byte IQ pair. Since the TigerSHARC link port transfers data in
quad-word (16-byte) blocks, four IQ pairs can make up one quad-
word. If the channel data is selected (Bit 0 = 0 of 0x1B/0x1D),
4-byte IQ words of the four channels can be output in succession or
alternating channel pair IQ words can be output. Figures 41
and 42 show the quad-word transmitted for each scenario with
corresponding register values for configuring each link port.
If AGC output is selected (Bit 0 = 1), RSSI information can be
sent with the IQ pair from each AGC. Each link port can be
configured to output data from one AGC or both link ports can
output data from the same AGC. If both link ports are transmitting
the same data, RSSI information must be sent with the IQ
words (Bit 2 = 0). Note that the actual RSSI word is only two
bytes (12 bits appended with four zeros), so the link port sends
two bytes of 0s immediately after each RSSI word to make a full
16-byte quad-word.
LINK PORT A
LINK PORT B
LINK PORT
A OR B
Figure 40. Link Port Connection between AD6634
and TigerSHARC
Figure 41. Link Port Data from RCF
(4 BYTES)
(4 BYTES)
(4 BYTES)
CH 0 I, Q
CH 0 I, Q
CH 2 I, Q
AD6634
LCLKOUT
LCLKIN
PCLK
LDAT
ADDR 0x1B OR 0x1D BIT 0 = 0, BIT 1 = 0
ADDR 0x1B OR 0x1D BIT 0 = 0, BIT 1 = 1
(4 BYTES)
(4 BYTES)
(4 BYTES)
CH 1 I, Q
CH 1 I, Q
CH 3 I, Q
8
(4 BYTES)
(4 BYTES)
(4 BYTES)
CH 2 I, Q
CH 0 I, Q
CH 2 I, Q
LCLKIN
LCLKOUT
LDAT
TigerSHARC
PCLK
AD6634
(4 BYTES)
(4 BYTES)
(4 BYTES)
CH 3 I, Q
CH 1 I, Q
CH 3 I, Q