ADAU1445YSVZ-3A-RL Analog Devices Inc, ADAU1445YSVZ-3A-RL Datasheet - Page 6

• Manufacturer Part Number: ADAU1445YSVZ-3A-RL
• Description: 175MHZ SigmaDSP,2x8 SRCs
• Manufacturer: Analog Devices Inc
• Series: SigmaDSP®r
• Type: Audio Processorr

Specifications of ADAU1445YSVZ-3A-RL

• Applications: Automotive Audio
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP Exposed Pad, 100-eTQFP, 100-HTQFP, 100-VQFP
• Format: Fixed Point
• Program Memory Size: Not RequiredKB
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Temp Range: -40C to 105C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADAU1442/ADAU1445/ADAU1446
Parameter
CRYSTAL OSCILLATOR
REGULATOR
1
2
AVDD = 3.3 V ± 10%, DVDD = 1.8 V ± 10%, PVDD = 3.3 V, IOVDD = 3.3 V ± 10%, T
core clock f
Table 3.
Parameter
ANALOG PERFORMANCE
DIGITAL I/O
POWER
To calculate the group delay, refer to the SRC Group Delay section.
Regulator specifications are calculated using an NJT4030P transistor from On Semiconductor in the circuit.
I/O Sample Rate Ratio
THD + N
Transconductance
DVDD Voltage
Auxiliary Analog Inputs
Input Voltage, High (V
Input Voltage, Low (V
Input Leakage, High (I
Input Leakage, Low (I
High Level Output Voltage (V
Low Level Output Voltage (V
Input Capacitance (C
Multipurpose Pins Output Drive
Supply Voltage
Supply Current
Resolution
Full-Scale Analog Input
Integral Nonlinearity (INL)
Differential Nonlinearity (DNL)
Gain Error
Input Impedance
Sample Rate
Analog Voltage (AVDD)
Digital Voltage (DVDD)
PLL Voltage (PVDD)
IOVDD Voltage (IOVDD)
Analog Current (AVDD)
CORE
2
= 172.032 MHz, I/O pins set to 2 mA drive setting, unless otherwise noted.
I
IL
)
IL
IH
IH
) at 0 V
)
)
) at 3.3 V
OL
OH
)
)
Min
1:8
1.65
Min
−2.3
−2.0
−2.0
0.7 × IOVDD
−2
−2
60
−85
−2
−8
−140
0.85 × IOVDD
2.97
1.62
2.97
2.97
Rev. C | Page 6 of 92
Typ
−133
40
1.75
Typ
10
AVDD
200
f
5
2
3.3
1.8
3.3
3.3
2
CORE
/896
Max
7.75:1
−120
1.85
Max
+2.3
+2.0
+2.0
0.3 × IOVDD
+2
+8
140
−10
+2
+2
−60
0.1 × IOVDD
3.63
1.98
3.63
3.63
A
= −40°C to +105°C, master clock input = 12.288 MHz,
Unit
dB
mS
V
Unit
Bits
V
LSB
LSB
LSB
kΩ
kHz
V
V
μA
μA
μA
μA
μA
μA
μA
V
V
pF
mA
V
V
V
V
mA
Test Conditions/Comments
Maximum 500 mA load.
Test Conditions/Comments
AVDD = 3.3 V ± 10%.
4:1 multiplexed input, each
channel at f
f
channel is sampled at 48 kHz.
Digital input pins except
SPDIFI.
Digital input pins except
SPDIFI.
Digital input pins except
MCLK and SPDIFI.
MCLK.
SPDIFI.
All other pins.
CLKMODEx, RSVD, PLLx,
RESET.
MCLK.
SPDIFI.
I
I
Guaranteed by design.
These pins are not designed
for static current draw and
should not drive LEDs directly.
OH
OL
CORE
= 1 mA.
= 1 mA.
= 172.032 MHz, each
1
1
CORE
/3584. For