ADAU1445YSVZ-3A-RL Analog Devices Inc, ADAU1445YSVZ-3A-RL Datasheet - Page 68

• Manufacturer Part Number: ADAU1445YSVZ-3A-RL
• Description: 175MHZ SigmaDSP,2x8 SRCs
• Manufacturer: Analog Devices Inc
• Series: SigmaDSP®r
• Type: Audio Processorr

Specifications of ADAU1445YSVZ-3A-RL

• Applications: Automotive Audio
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP Exposed Pad, 100-eTQFP, 100-HTQFP, 100-VQFP
• Format: Fixed Point
• Program Memory Size: Not RequiredKB
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Temp Range: -40C to 105C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADAU1442/ADAU1445/ADAU1446
Enable S/PDIF to I
Table 64. Bit Descriptions of Register 0xE241
Bit Position
[15:3]
2
1
0
The S/PDIF receiver can be set to send the stereo audio stream
and the auxiliary S/PDIF bits in I
the 12 MP pins. The eight outputs are divided into two groups:
Group 1 converts S/PDIF to I
signals), and Group 2 decodes the channel status and user data
bits (virtual LRCLK, user data, channel status, validity bit, and
block start signal).
LRCLKx
Description
Reserved
Output mode
0 = I
1 = TDM
Group 2 enable
0 = Group 2 off
1 = Group 2 on
Group 1 enable
0 = Group 1 off
1 = Group 1 on
2
2
S Output Register (Address 0
S
2
LEFT AUDIO DECODE
S (LRCLK, BCLK, and SDATA
2
0
24 BITS: LEFT AUDIO
S or TDM format on eight of
1
0
BITS
xE241)
2
Default
0
0
0
Figure 54. S/PDIF TD
Rev. C | Page 68 of 92
7 DECODED
BITS
3
FRAME
RIG
This MP output is controlled by setting three bits in
Register 0xE241:
•
•
•
When S/PDIF to I
are used.
When TDM mode is active, Slot 0 and Slot 4 contain the audio
data, and Slot 1 contains the streamed block start, ch
user
in real tim
seven M
sp
Ta
Bit Position
31
30
29
28
27
26
25
[24:0]
M Signal
HT AUDIO
onding TD
4
ble 65. Fu
1
Bit 0 switches Group 1 on and off.
Bit 1 switches Group 2 on and off.
Bit 2 switches between I
data, and validity bits (see Table 65). The bits are streamed
SBs
e a
of Slot 1 ar
nction of Decoded Bits in Figure 54
5
nd are synchr
M format is shown in more detail in Figu
24 BITS: RIGHT AUDIO
2
S mode is active, the pins described in Table 53
Description
Block start (high for first 16 samples)
Channel status of right channel
Channel status of left channel
User data bit, right channel
User data bit, left channel
Validity bit, right channel
Validity bit, left channel
Not used
e used, as shown in Table 65. The corre-
6
onized to the audio data. Only the
2
4
S and TDM modes.
7
annel status,
re 54.