ADAU1445YSVZ-3A-RL Analog Devices Inc, ADAU1445YSVZ-3A-RL Datasheet - Page 78

• Manufacturer Part Number: ADAU1445YSVZ-3A-RL
• Description: 175MHZ SigmaDSP,2x8 SRCs
• Manufacturer: Analog Devices Inc
• Series: SigmaDSP®r
• Type: Audio Processorr

Specifications of ADAU1445YSVZ-3A-RL

• Applications: Automotive Audio
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP Exposed Pad, 100-eTQFP, 100-HTQFP, 100-VQFP
• Format: Fixed Point
• Program Memory Size: Not RequiredKB
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Temp Range: -40C to 105C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADAU1442/ADAU1445/ADAU1446
SERIAL OUTPUT FLEXIBLE TDM INTERFACE
MODES AND SETTINGS
The flexib
input port
output p
output p
For this
sponding
In flexib
32 byte
clock. C
of 64 by
It is imp
must be
individ
stream.
data fro
starts w
Because t
formats, a sin
one slot
audio c
occupies t
(Input C
middle, o
TDM sl
mode o
In this e
output channels to a flexible TDM stream. Output Channel 0 is
s (slots) of
ually assign
m any of th
hannel occ
n the outpu
ith Output
ot register. An example o
. An 8-bit a
tes in the f
Each of th
ombining t
xample, th
mode to b
le TDM m
ortant to n
o
orts in flexi
hannels[2
routed as
he audio
serial por
r least sig
rts. There a
hree slot
le TDM m
s can als
SDATA_OU
SDATA_OU
gle c
LRCL
inform
hannel o
e 64 TD
ese 24 o
upies t
o be u
e activ
ts must
lexible
3:0]) a
data ca
s. To s
ree mo
ode, e
stereo
ed to d
nifican
ote th
Chann
udio c
t side i
he tw
Kx
T0
T1
ble TD
ode used on the SDATA_IN[1:0] serial
re 24 o
...
...
sed on
ach flex
o serial
at, unli
wo slot
et up ea
e, the w
nd byte
31
63
ation fo
hannel
stream
pairs,
nocha
ifferen
utput c
n be in
s show
el 0 an
t) mus
be set
M out
f aud
M mo
utpu
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63
0
1
io data may occupy more than
nnels of audio are sent from the
the SDA
to 11 (TDM8 or flexible TDM).
ke in the FARM, where signals
the output channels can be
s, and a 24-bit audio channel
.
t places on the flexible TDM
put slots is capable of taking its
hannels, as long as data retrieval
d increases sequentially.
t be set in the corresponding
ible TDM stream includes
output ports allows for a total
put in 8-, 16-, or 24-bit
n in Figure 58.
t channels available to the
ord length bits of the corre-
ch slot, the supplying channel
f the flexible TDM interface
r every frame on the frame
occupies one slot, a 16-bit
position (most significant,
de.
2
3
4
TA_OUT[1:0] serial
5
Figure 57. Flexible TDM Interface Mode—Output Streams
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Rev. C | Page 78 of 92
FRAME
8 bits, Output Channe
24 bit. Th
output
the eight MSBs. Slot 11 is set to output the most significant
(MS) byte of Outp
middle (M) byte; t
the 16 MSBs of da
and Slot 44 are set
(M), and least sign
Channel 2, thus ac
system allows for
for any channel, b
M, LS format. Not
any slot, as long as
and increases sequ
with the automatic
Automatic Output
Two slots are cont
bits control the hig
lower slot. For exa
TDM Slot 0 and T
and Bits[7:0] cont
A special conditio
slots can only be u
and cannot be use
more than eight b
The default setting
channel is configur
and does not use t
the most significant (MS) byte of Output Channel 0, or
e target slots are set up accordingly. Slot 3 is set to
any order or com
its of data.
ut most applicatio
rol TDM Slot 0.
ta from Output C
ained within each
n applies to Slot 3
d in conjunction
e that any output
mple, in Register
DM Slot 1, Bits[1
he flexible TDM
ut Channel 1, and Slot 12 is
herefore, Slot 11
sed to hold the M
counting for all 2
to output the mo
ificant (LS) bytes, r
entially. This is d
ed in the standar
assignment begi
Channel Assignme
her slot, and the
of all 16 bits hig
output channel
l 1 is 16 bits, and Output Channel 2 is
bination of slots to be used
and Slot 12 together output
ns with Output Channel 0
assignment (see the
h (0xFFFF) indicates that the
d serial input interface mode
interface mode.
with other slots to hold
one to ensure compatibility
5:8] control TDM Slot 1,
hannel 1. Slot 42, Slot 43,
st significant (MS), middle
lower eight bits control the
4 bits. The flexibility of the
channel can be assigned to
0xE1C0 (SDATA_OUT0)
1 and Slot 63. These two
ns follow a sequential MS,
S byte of an 8-bit channel
register. The upper eight
espectively, of Output
nt section).
32
0
set to output the
...
...