ADV7393-DBRDZ Analog Devices Inc, ADV7393-DBRDZ Datasheet - Page 47

• Manufacturer Part Number: ADV7393-DBRDZ
• Description: EVALUATION BOARD I.C.
• Manufacturer: Analog Devices Inc
• Series: Advantiv®r

Specifications of ADV7393-DBRDZ

• Design Resources: Reconstruction Video Filter Using ADA4430-1 Amplifier After ADV7393 Video Encoder (CN0101)
• Main Purpose: Video, Video Encoder
• Utilized Ic / Part: ADV7393
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ENHANCED DEFINITION/HIGH DEFINITION
Subaddress 0x01, Bits[6:4] = 001 or 010
ED or HD YCrCb data can be input in a 4:2:2 format over an
8-/10-bit DDR bus or a 16-bit SDR bus.
The clock signal must be provided on the CLKIN pin. If
required, external synchronization signals can be provided on
the HSYNC and VSYNC pins. Embedded EAV/SAV timing
codes are also supported.
16-Bit 4:2:2 YCrCb Mode (SDR)
In 16-bit 4:2:2 YCrCb input mode, the Y pixel data is input on
Pin P15 to Pin P8, with P8 being the LSB.
The CrCb pixel data is input on Pin P7 to Pin P0, with Pin P0
being the LSB.
8-/10-Bit 4:2:2 YCrCb Mode (DDR)
In 8-/10-bit DDR 4:2:2 YCrCb input mode, the Y pixel data is
input on Pin P15 to Pin P8/P6 on either the rising or falling
edge of CLKIN. Pin P8/P6 is the LSB.
The CrCb pixel data is also input on Pin P15 to Pin P8/P6
on the opposite edge of CLKIN. P8/P6 is the LSB.
The 10-bit mode is enabled using Subaddress 0x33, Bit 2.
Whether the Y data is clocked in on the rising or falling edge of
CLKIN is determined by Subaddress 0x01, Bits[2:1] (see Figure 57
and Figure 58).
NOTES
1. SUBADDRESS 0x01 [2:1] SHOULD BE SET TO 00 IN THIS CASE.
2. 10-BIT MODE IS ENABLED USING SUBADDRESS 0x33, BIT 2.
NOTES
1. SUBADDRESS 0x01 [2:1] SHOULD BE SET TO 11 IN THIS CASE.
2. 10-BIT MODE IS ENABLED USING SUBADDRESS 0x33, BIT 2.
P[15:P6]
P[15:8]/
P]15:6]
P[15:8]/
CLKIN
CLKIN
Figure 57. ED/HD-DDR Input Sequence (EAV/SAV)—Option A
Figure 58. ED/HD-DDR Input Sequence (EAV/SAV)—Option B
3FF
3FF
00
00
00
00
X Y
XY
Cb0
Y0
Y0
Cb0
Cr0
Y1
Y1
Cr0
Rev. B | Page 47 of 108
ENHANCED DEFINITION (AT 54 MHz)
Subaddress 0x01, Bits[6:4] = 111
ED YCrCb data can be input in an interleaved 4:2:2 format on
an 8-/10-bit bus at a rate of 54 MHz.
A 54 MHz clock signal must be provided on the CLKIN pin.
Embedded EAV/SAV timing codes are supported. External
synchronization signals are not supported in this mode.
The interleaved pixel data is input on Pin P15 to Pin P8/P6,
with Pin P8/P6 being the LSB.
The 10-bit mode is enabled using Subaddress 0x33, Bit 2.
P[15:8]/P[15:6]
NOTES
1. 10-BIT MODE IS ENABLED USING SUBADDRESS 0x33, BIT 2.
ADV7390/ADV7391/ADV7392/ADV7393
CLKIN
Figure 61. ED (at 54 MHz) Input Sequence (EAV/SAV)
INTERLACED TO
PROGRESSIVE
INTERLACED TO
DECODER
PROGRESSIVE
INTERLACED TO
Figure 62. ED (at 54 MHz) Example Application
PROGRESSIVE
MPEG2
DECODER
YCrCb
Figure 60. ED/HD-DDR Example Application
Figure 59. ED/HD-SDR Example Application
DECODER
M PEG2
YCrCb
MPEG2
YCrCb
3FF
00
54MHz
YCrCb
YCrCb
CrCb
Y
00
8/10
8/10
8
8
2
2
2
XY
CLKIN
P[7:0]
P[15:8]
VSYNC
HSYNC
VSYNC,
HSYNC
CLKIN
P[15:8]/P[15:6]
ADV7392/
ADV7393
CLKIN
P[15:8]/P[15:6]
VSYNC
HSYNC
ADV7392/
ADV7393
Cb0
ADV7392/
ADV7393
Y0
Cr0
Y1