ADV7393-DBRDZ Analog Devices Inc, ADV7393-DBRDZ Datasheet - Page 10

• Manufacturer Part Number: ADV7393-DBRDZ
• Description: EVALUATION BOARD I.C.
• Manufacturer: Analog Devices Inc
• Series: Advantiv®r

Specifications of ADV7393-DBRDZ

• Design Resources: Reconstruction Video Filter Using ADA4430-1 Amplifier After ADV7393 Video Encoder (CN0101)
• Main Purpose: Video, Video Encoder
• Utilized Ic / Part: ADV7393
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADV7390/ADV7391/ADV7392/ADV7393
DIGITAL TIMING SPECIFICATIONS—1.8 V
V
All specifications T
Table 10.
Parameter
VIDEO DATA AND VIDEO CONTROL PORT
PIPELINE DELAY
RESET CONTROL
1
2
3
4
5
SD = standard definition, ED = enhanced definition (525p/625p), HD = high definition, SDR = single data rate, DDR = dual data rate.
Video data: P[15:0] for ADV7392/ADV7393 or P[7:0] for ADV7390/ADV7391.
Video control: HSYNC and VSYNC .
Guaranteed by characterization.
Guaranteed by design.
DD
Data Input Setup Time, t
Data Input Hold Time, t
Control Input Setup Time, t
Control Input Hold Time, t
Control Output Access Time, t
Control Output Hold Time, t
SD
ED
HD
RESET Low Time
= 1.71 V to 1.89 V, PV
CVBS/Y-C Outputs (2×)
CVBS/Y-C Outputs (8×)
CVBS/Y-C Outputs (16×)
Component Outputs (2×)
Component Outputs (8×)
Component Outputs (16×)
Component Outputs (1×)
Component Outputs (4×)
Component Outputs (8×)
Component Outputs (1×)
Component Outputs (2×)
Component Outputs (4×)
1
1
1
5
MIN
to T
12
11
DD
4
MAX
4
12
11
= 1.71 V to 1.89 V, V
4
14
4
(−40°C to +85°C), unless otherwise noted.
4
13
4
2, 3
AA
Conditions
SD
ED/HD-SDR
ED/HD-DDR
ED (at 54 MHz)
SD
ED/HD-SDR
ED/HD-DDR
ED (at 54 MHz)
SD
ED/HD-SDR or ED/HD-DDR
ED (at 54 MHz)
SD
ED/HD-SDR or ED/HD-DDR
ED (at 54 MHz)
SD
ED/HD-SDR, ED/HD-DDR, or ED (at 54 MHz)
SD
ED/HD-SDR, ED/HD-DDR, or ED (at 54 MHz)
SD oversampling disabled
SD oversampling enabled
SD oversampling enabled
SD oversampling disabled
SD oversampling enabled
SD oversampling enabled
ED oversampling disabled
ED oversampling enabled
ED oversampling enabled
HD oversampling disabled
HD oversampling enabled
HD oversampling enabled
= 2.6 V to 3.465 V, V
Rev. B | Page 10 of 108
1
DD_IO
= 1.71 V to 1.89 V.
Min
1.4
1.9
1.9
1.6
1.4
1.5
1.5
1.3
1.4
1.4
4.0
5.0
100
1.2
1.0
1.0
1.0
Typ
68
79
67
78
69
84
41
49
46
40
42
44
Max
13
12
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Clock cycles
Clock cycles
Clock cycles
Clock cycles
Clock cycles
Clock cycles
Clock cycles
Clock cycles
Clock cycles
Clock cycles
Clock cycles
Clock cycles
ns