ADV7393-DBRDZ Analog Devices Inc, ADV7393-DBRDZ Datasheet - Page 15

• Manufacturer Part Number: ADV7393-DBRDZ
• Description: EVALUATION BOARD I.C.
• Manufacturer: Analog Devices Inc
• Series: Advantiv®r

Specifications of ADV7393-DBRDZ

• Design Resources: Reconstruction Video Filter Using ADA4430-1 Amplifier After ADV7393 Video Encoder (CN0101)
• Main Purpose: Video, Video Encoder
• Utilized Ic / Part: ADV7393
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIXEL PORT
a(MIN) = 244 CLOCK CYCLES FOR 525p.
a(MIN) = 264 CLOCK CYCLES FOR 625p.
b = PIPELINE DELAY. PLEASE REFER TO RELEVANT PIPELINE DELAY. THIS CAN BE FOUND IN THE DIGITAL TIMING
A FALLING EDGE OF HSYNC INTO THE ENCODER GENERATES A SYNC FALLING EDGE ON THE OUTPUT AFTER A TIME
EQUAL TO THE PIPELINE DELAY.
PIXEL PORT*
a = AS PER RELEVANT STANDARD.
b = PIPELINE DELAY. PLEASE REFER TO RELEVANT PIPELINE DELAY. THIS CAN BE FOUND IN THE DIGITAL TIMING
A FALLING EDGE OF HSYNC INTO THE ENCODER GENERATES A SYNC FALLING EDGE ON THE OUTPUT AFTER A TIME
EQUAL TO THE PIPELINE DELAY.
PIXEL PORT
Y OUTPUT
Y OUTPUT
SPECIFICATION SECTION OF THE DATA SHEET.
SPECIFICATION SECTION OF THE DATA SHEET.
HSYNC
VSYNC
HSYNC
VSYNC
Figure 13. ED-DDR, 8-/10-Bit 4:2:2 YCrCb ( HSYNC / VSYNC ) Input Timing Diagram
Figure 12. ED-SDR, 16-Bit 4:2:2 YCrCb ( HSYNC / VSYNC ) Input Timing Diagram
b
b
Rev. B | Page 15 of 108
a
a
ADV7390/ADV7391/ADV7392/ADV7393
Cb0
Y0
Cb0
Cr0
Y1
Y0
Cb2
Y2
Cr0
Cr2
Y3
Y1