ADV7393-DBRDZ Analog Devices Inc, ADV7393-DBRDZ Datasheet - Page 99

• Manufacturer Part Number: ADV7393-DBRDZ
• Description: EVALUATION BOARD I.C.
• Manufacturer: Analog Devices Inc
• Series: Advantiv®r

Specifications of ADV7393-DBRDZ

• Design Resources: Reconstruction Video Filter Using ADA4430-1 Amplifier After ADV7393 Video Encoder (CN0101)
• Main Purpose: Video, Video Encoder
• Utilized Ic / Part: ADV7393
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ENHANCED DEFINITION
Table 99. ED Configuration Scripts
Input Format
525p
525p
525p
525p
525p
525p
525p
525p
625p
625p
625p
625p
625p
625p
625p
625p
Table 100. 16-Bit 525p YCrCb In (EAV/SAV), YPrPb Out
Subaddress
0x17
0x00
0x01
0x30
0x31
Table 101. 16-Bit 525p YCrCb In, YPrPb Out
Subaddress
0x17
0x00
0x01
0x30
0x31
Table 102. 16-Bit 525p YCrCb In (EAV/SAV), RGB Out
Subaddress
0x17
0x00
0x01
0x02
0x30
0x31
Setting
0x02
0x1C
0x10
0x04
0x01
Setting
0x02
0x1C
0x10
0x00
0x01
Setting
0x02
0x1C
0x10
0x10
0x04
0x01
Input Data Width
8-bit DDR
8-bit DDR
10-bit DDR
10-bit DDR
16-bit SDR
16-bit SDR
16-bit SDR
16-bit SDR
8-bit DDR
8-bit DDR
10-bit DDR
10-bit DDR
16-bit SDR
16-bit SDR
16-bit SDR
16-bit SDR
Description
Software reset.
All DACs enabled. PLL enabled (8×).
ED-SDR input mode.
525p
zation. EIA-770.2 output levels.
Pixel data valid.
Description
Software reset.
All DACs enabled. PLL enabled (8×).
ED-SDR input mode.
525p at 59.94 Hz. HSYNC/VSYNC synch-
ronization. EIA-770.2 output levels.
Pixel data valid.
Description
Software reset.
All DACs enabled. PLL enabled (8×).
ED-SDR input mode.
RGB output enabled. RGB output sync
enabled.
525p at 59.94 Hz. EAV/SAV synchroni-
zation. EIA-770.2 output levels.
Pixel data valid.
at
59.94 Hz. EAV/SAV synchroni-
Synchronization Format
EAV/SAV
EAV/SAV
EAV/SAV
EAV/SAV
EAV/SAV
HSYNC / VSYNC
EAV/SAV
HSYNC / VSYNC
EAV/SAV
EAV/SAV
EAV/SAV
EAV/SAV
EAV/SAV
HSYNC / VSYNC
EAV/SAV
HSYNC / VSYNC
Rev. B | Page 99 of 108
Input Color Space
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
Table 103. 16-Bit 525p YCrCb In, RGB Out
Subaddress
0x17
0x00
0x01
0x02
0x30
0x31
Table 104. 16-Bit 625p YCrCb In (EAV/SAV), YPrPb Out
Subaddress
0x17
0x00
0x01
0x30
0x31
Table 105. 16-Bit 625p YCrCb In, YPrPb Out
Subaddress
0x17
0x00
0x01
0x30
0x31
ADV7390/ADV7391/ADV7392/ADV7393
Setting
0x02
0x1C
0x10
0x10
0x00
0x01
Setting
0x02
0x1C
0x10
0x1C
0x01
Setting
0x02
0x1C
0x10
0x18
0x01
Output Color Space
YPrPb
RGB
YPrPb
RGB
YPrPb
YPrPb
RGB
RGB
YPrPb
RGB
YPrPb
RGB
YPrPb
YPrPb
RGB
RGB
Description
Software reset.
All DACs enabled. PLL enabled (8×).
ED-SDR input mode.
RGB output enabled. RGB output sync
enabled.
525p at 59.94 Hz. HSYNC/VSYNC synch-
ronization. EIA-770.2 output levels.
Pixel data valid.
Description
Software reset.
All DACs enabled. PLL enabled (8×).
ED-SDR input mode.
625p at 50 Hz. EAV/SAV synchroni-
zation. EIA-770.2 output levels.
Pixel data valid.
Description
Software reset.
All DACs enabled. PLL enabled (8×).
ED-SDR input mode.
625p at 50 Hz. HSYNC/VSYNC synch-
ronization. EIA-770.2 output levels.
Pixel data valid.
Table Number
Table 108
Table 110
Table 109
Table 111
Table 100
Table 101
Table 102
Table 103
Table 112
Table 114
Table 113
Table 115
Table 104
Table 105
Table 106
Table 107