ADV7393-DBRDZ Analog Devices Inc, ADV7393-DBRDZ Datasheet - Page 38

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ADV7393-DBRDZ

Manufacturer Part Number
ADV7393-DBRDZ
Description
EVALUATION BOARD I.C.
Manufacturer
Analog Devices Inc
Series
Advantiv®r
Datasheet

Specifications of ADV7393-DBRDZ

Design Resources
Reconstruction Video Filter Using ADA4430-1 Amplifier After ADV7393 Video Encoder (CN0101)
Main Purpose
Video, Video Encoder
Utilized Ic / Part
ADV7393
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Secondary Attributes
-
Embedded
-
Primary Attributes
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
ADV7390/ADV7391/ADV7392/ADV7393
Table 28. Register 0x84 to Register 0x87
SR7 to
SR0
0x84
0x86
0x87
1
2
When set to 0, the horizontal/vertical counters automatically wrap around at the end of the line/field/frame of the selected standard. When set to 1, the
horizontal/vertical counters are free running and wrap around when external sync signals indicate to do so.
Available on the ADV7392/ADV7393 (40-pin devices) only.
Register
SD Mode
Register 4
SD Mode
Register 5
SD Mode
Register 6
Bit Description
Reserved
SD SFL/SCR/TR mode select
SD active video length
SD chroma
SD burst
SD color bars
SD luma/chroma wwap
NTSC color subcarrier adjust (delay from
the falling edge of output HSYNC pulse to
the start of color burst)
Reserved
SD EIA/CEA-861B synchronization
compliance
Reserved
SD horizontal/vertical counter mode
SD RGB color swap
SD luma and color scale control
SD luma scale saturation
SD hue adjust
SD brightness
SD luma SSAF gain
SD input standard autodetection
Reserved
SD RGB input enable
2
2
1
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0
1
0
1
0
1
7
6
0
1
0
1
0
5
0
1
0
0
1
Bit Number
4
0
1
0
0
1
3
1
0
1
0
1
0
2
0
0
1
1
0
0
1
1
0
1
0
1
0
0
1
1
0
1
0
0
0
1
0
1
0
1
Register Setting
Disabled.
Subcarrier reset mode enabled.
Timing reset mode enabled.
SFL mode enabled.
720 pixels.
710 (NTSC), 702 (PAL).
Chroma enabled.
Chroma disabled.
Enabled.
Disabled.
Disabled.
Enabled.
DAC 2 = luma, DAC 3 = chroma.
DAC 2 = chroma, DAC 3 = luma.
5.17 μs.
5.31 μs.
5.59 μs (must be set for
Macrovision compliance).
Reserved.
Disabled.
Enabled.
Update field/line counter.
Field/line counter free running.
Normal.
Color reversal enabled.
Disabled.
Enabled.
Disabled.
Enabled.
Disabled.
Enabled.
Disabled.
Enabled.
Disabled.
Enabled.
Disabled.
Enabled.
0 must be written to this bit.
SD YCrCb input.
SD RGB input.
Reset
Value
0x00
0x02
0x00

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