DSPIC33FJ32MC204-E/ML Microchip Technology, DSPIC33FJ32MC204-E/ML Datasheet - Page 175
![16-bit DSC, 32KB Flash,Motor,40 MIPS,nanoWatt 44 QFN 8x8x0.9mm TUBE](/photos/6/81/68122/150-44-qfn_sml.jpg)
DSPIC33FJ32MC204-E/ML
Manufacturer Part Number
DSPIC33FJ32MC204-E/ML
Description
16-bit DSC, 32KB Flash,Motor,40 MIPS,nanoWatt 44 QFN 8x8x0.9mm TUBE
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Datasheets
1.DSPIC33FJ32MC202-IMM.pdf
(320 pages)
2.DSPIC33FJ32MC202-IMM.pdf
(14 pages)
3.DSPIC33FJ32MC202-IMM.pdf
(14 pages)
Specifications of DSPIC33FJ32MC204-E/ML
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
35
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 9x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
44-QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- DSPIC33FJ32MC202-IMM PDF datasheet
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- DSPIC33FJ32MC202-IMM PDF datasheet #3
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REGISTER 16-1:
© 2011 Microchip Technology Inc.
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10-8
bit 7
bit 6
bit 5
CNTERR
SWPAB
R/W-0
R/W-0
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304
CNTERR: Count Error Status Flag bit
1 = Position count error has occurred
0 = No position count error has occurred
Unimplemented: Read as ‘0’
QEISIDL: Stop in Idle Mode bit
1 = Discontinue module operation when device enters Idle mode
0 = Continue module operation in Idle mode
INDEX: Index Pin State Status bit (Read-Only)
1 = Index pin is High
0 = Index pin is Low
UPDN: Position Counter Direction Status bit
1 = Position Counter Direction is positive (+)
0 = Position Counter Direction is negative (-)
QEIM<2:0>: Quadrature Encoder Interface Mode Select bits
111 = Quadrature Encoder Interface enabled (x4 mode) with position counter reset by match
110 = Quadrature Encoder Interface enabled (x4 mode) with Index Pulse reset of position counter
101 = Quadrature Encoder Interface enabled (x2 mode) with position counter reset by match
100 = Quadrature Encoder Interface enabled (x2 mode) with Index Pulse reset of position counter
011 = Unused (Module disabled)
010 = Unused (Module disabled)
001 = Starts 16-bit Timer
000 = Quadrature Encoder Interface/Timer off
SWPAB: Phase A and Phase B Input Swap Select bit
1 = Phase A and Phase B inputs swapped
0 = Phase A and Phase B inputs not swapped
PCDOUT: Position Counter Direction State Output Enable bit
1 = Position Counter Direction Status Output Enable (QEI logic controls state of I/O pin)
0 = Position Counter Direction Status Output Disabled (Normal I/O pin operation)
TQGATE: Timer Gated Time Accumulation Enable bit
1 = Timer gated time accumulation enabled
0 = Timer gated time accumulation disabled
PCDOUT
Note:
R/W-0
(Read-only bit when QEIM<2:0> = ‘1XX’)
(Read/Write bit when QEIM<2:0> = ‘001’)
U-0
—
QEIxCON: QEI CONTROL REGISTER
(MAXCNT)
(MAXCNT)
CNTERR flag only applies when QEIM<2:0> = ‘110’ or ‘100’.
‘1’ = Bit is set
W = Writable bit
TQGATE
QEISIDL
R/W-0
R/W-0
INDEX
R/W-0
R-0
TQCKPS<1:0>
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/W-0
UPDN
R/W-0
POSRES
R/W-0
R/W-0
x = Bit is unknown
QEIM<2:0>
R/W-0
R/W-0
TQCS
DS70283H-page 175
UPDN_SRC
R/W-0
R/W-0
bit 8
bit 0
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