DSPIC33FJ32MC204-E/ML Microchip Technology, DSPIC33FJ32MC204-E/ML Datasheet - Page 304
![16-bit DSC, 32KB Flash,Motor,40 MIPS,nanoWatt 44 QFN 8x8x0.9mm TUBE](/photos/6/81/68122/150-44-qfn_sml.jpg)
DSPIC33FJ32MC204-E/ML
Manufacturer Part Number
DSPIC33FJ32MC204-E/ML
Description
16-bit DSC, 32KB Flash,Motor,40 MIPS,nanoWatt 44 QFN 8x8x0.9mm TUBE
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Datasheets
1.DSPIC33FJ32MC202-IMM.pdf
(320 pages)
2.DSPIC33FJ32MC202-IMM.pdf
(14 pages)
3.DSPIC33FJ32MC202-IMM.pdf
(14 pages)
Specifications of DSPIC33FJ32MC204-E/ML
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
35
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 9x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
44-QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304
Revision C (June 2008)
This revision includes minor typographical and
formatting changes throughout the data sheet text.
The major changes are referenced by their respective
section in the following table.
TABLE A-1:
DS70283H-page 304
“High-Performance, 16-bit Digital
Signal Controllers”
Section 1.0 “Device Overview”
Section 4.0 “Memory Organization”
Section 6.0 “Resets”
Section 8.0 “Oscillator
Configuration”
Section 9.0 “Power-Saving
Features”
Section 10.0 “I/O Ports”
Section 14.0 “Output Compare”
Section Name
MAJOR SECTION UPDATES
Added Extended Interrupts column to Remappable Peripherals in the
Controller Families table and Note 3 (see Table 1).
Added Note 1 to all pin diagrams, which references RPn pin usage by
remappable peripherals (see “Pin Diagrams”).
Changed PORTA pin name from RA15 to RA10 (see Table 1-1).
Added SFR definitions (ACCAL, ACCAH, ACCAU, ACCBL, ACCBH, and
ACCBU) to the CPU Core Register Map (see Table 4-1).
Updated Reset value for CORCON (see Table 4-1).
Updated Reset values for the following SFRs: IPC1, IPC3-IPC5, IPC7,
IPC16, and INTTREG (see Table 4-4).
Updated all SFR names in QEI1 Register Map (see Table 4-10).
Updated the bit range for AD1CON3 from ADCS<5:0> to ADCS<7:0>) (see
Table 4-14 and Table 4-15).
Updated the Reset value for CLKDIV in the System Control Register Map
(see Table 4-23).
Entire section was replaced to maintain consistency with other dsPIC33F
data sheets.
Removed the first sentence of the third clock source item (External Clock) in
Section 8.1.1.2 “Primary”.
Updated the default bit values for DOZE and FRCDIV in the Clock Divisor
Register (see Register 8-2).
Added the center frequency in the OSCTUN register for the FRC Tuning bits
(TUN<5:0>) value 011111 and updated the center frequency for bits value
011110 (see Register 8-4).
Added the following two registers:
• PMD1: Peripheral Module Disable Control Register 1
• PMD2: Peripheral Module Disable Control Register 2
• PMD3: Peripheral Module Disable Control Register 3
Added paragraph and Table 10-1 to Section 10.2 “Open-Drain
Configuration”, which provides details on I/O pins and their functionality.
Removed the following sections, which are now available in the related
section of the dsPIC33F/PIC24H Family Reference Manual:
• 9.4.2 “Available Peripherals”
• 9.4.3.3 “Mapping”
• 9.4.5 “Considerations for Peripheral Pin Selection”
Replaced sections 13.1, 13.2, and 13.3 and related figures and tables with
entirely new content.
Update Description
© 2011 Microchip Technology Inc.
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