DSPIC33FJ32MC204-E/ML Microchip Technology, DSPIC33FJ32MC204-E/ML Datasheet - Page 68
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DSPIC33FJ32MC204-E/ML
Manufacturer Part Number
DSPIC33FJ32MC204-E/ML
Description
16-bit DSC, 32KB Flash,Motor,40 MIPS,nanoWatt 44 QFN 8x8x0.9mm TUBE
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Datasheets
1.DSPIC33FJ32MC202-IMM.pdf
(320 pages)
2.DSPIC33FJ32MC202-IMM.pdf
(14 pages)
3.DSPIC33FJ32MC202-IMM.pdf
(14 pages)
Specifications of DSPIC33FJ32MC204-E/ML
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
35
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 9x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
44-QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- DSPIC33FJ32MC202-IMM PDF datasheet
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dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304
TABLE 6-2:
6.2
A Power-on Reset (POR) circuit ensures the device is
reset from power-on. The POR circuit is active until
V
has elapsed. The delay T
device bias circuits become stable.
The device supply voltage characteristics must meet
the
requirements to
Section 24.0 “Electrical Characteristics”
The POR status bit (POR) in the Reset Control register
(RCON<0>) is set to indicate the Power-on Reset.
DS70283H-page 68
V
T
V
T
T
T
DD
POR
BOR
PWRT
FSCM
POR
BOR
Note:
crosses the V
specified
Power-on Reset (POR)
When the device exits the Reset
condition (begins normal operation), the
device operating parameters (voltage,
frequency, temperature, etc.) must be
within their operating ranges, other-
wise the device may not function cor-
rectly.
ensure that the delay between the time
power is first applied, and the time
SYSRST becomes inactive, is long
enough to get all operating parameters
within specification.
Symbol
starting
OSCILLATOR DELAY
POR
generate
The
threshold and the delay T
user
voltage
POR
the
ensures the internal
application
POR.
POR threshold
POR extension time
BOR threshold
BOR extension time
Programmable power-up time delay
Fail-Safe Clock Monitor Delay
and
for details.
rise
Refer
must
POR
rate
Parameter
to
6.2.1
The on-chip regulator has a Brown-out Reset (BOR)
circuit that resets the device when the V
(V
circuit keeps the device in Reset until V
V
delay T
becomes stable.
The BOR status bit (BOR) in the Reset Control register
(RCON<1>) is set to indicate the Brown-out Reset.
The device will not run at full speed after a BOR as the
V
operation. The PWRT provides power-up time delay
(T
stabilized at the appropriate levels for full-speed
operation before the SYSRST is released.
The power-up timer delay (T
the
(FPWRT<2:0>) in the POR Configuration register
(FPOR<2:0>), which provides eight settings (from 0 ms
to 128 ms). Refer to
for further details.
Figure 6-3
reset delay (T
rises above the V
BOR
DD
PWRT
DD
should rise to acceptable levels for full-speed
Power-on
< V
threshold and the delay T
) to ensure that the system power supplies have
BOR
BOR
shows the typical brown-out scenarios. The
Brown-out Reset (BOR) and
Power-up timer (PWRT)
1.8V nominal
30 μs maximum
2.5V nominal
100 μs maximum
0-128 ms nominal
900 μs maximum
) for proper device operation. The BOR
ensures the voltage regulator output
BOR
BOR
Reset
+ T
Section 21.0 “Special Features”
PWRT
trip point
© 2011 Microchip Technology Inc.
Timer
) is initiated each time V
PWRT
Value
BOR
Value
) is programmed by
has elapsed. The
DD
Select
DD
is too low
crosses
bits
DD
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