DSPIC33FJ32MC204-E/ML Microchip Technology, DSPIC33FJ32MC204-E/ML Datasheet - Page 309
![16-bit DSC, 32KB Flash,Motor,40 MIPS,nanoWatt 44 QFN 8x8x0.9mm TUBE](/photos/6/81/68122/150-44-qfn_sml.jpg)
DSPIC33FJ32MC204-E/ML
Manufacturer Part Number
DSPIC33FJ32MC204-E/ML
Description
16-bit DSC, 32KB Flash,Motor,40 MIPS,nanoWatt 44 QFN 8x8x0.9mm TUBE
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Datasheets
1.DSPIC33FJ32MC202-IMM.pdf
(320 pages)
2.DSPIC33FJ32MC202-IMM.pdf
(14 pages)
3.DSPIC33FJ32MC202-IMM.pdf
(14 pages)
Specifications of DSPIC33FJ32MC204-E/ML
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
35
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 9x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
44-QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- DSPIC33FJ32MC202-IMM PDF datasheet
- DSPIC33FJ32MC202-IMM PDF datasheet #2
- DSPIC33FJ32MC202-IMM PDF datasheet #3
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- Download datasheet (5Mb)
Revision E (June 2009)
This revision includes minor typographical and
formatting changes throughout the data sheet text.
Global changes include:
• Changed all instances of OSCI to OSC1 and
• Changed all instances of PGCx/EMUCx and
Changed all instances of V
to V
All other major changes are referenced by their
respective section in the following table.
TABLE A-3:
© 2011 Microchip Technology Inc.
“High-Performance, 16-bit Digital Signal
Controllers”
Section 7.0 “Interrupt Controller”
Section 8.0 “Oscillator Configuration”
Section 10.0 “I/O Ports”
Section 17.0 “Serial Peripheral Interface (SPI)” Added Note 2 to the SPIx Control Register 1 (see Register 17-2).
Section 19.0 “Universal Asynchronous
Receiver Transmitter (UART)”
Section 24.0 “Electrical Characteristics”
OSCO to OSC2
PGDx/EMUDx (where x = 1, 2 or 3) to PGECx
and PGEDx
CAP
/V
DDCORE
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304
MAJOR SECTION UPDATES
Section Name
DDCORE
and V
DDCORE
/V
CAP
Added Note 2 to the 28-Pin QFN-S and 44-Pin QFN pin
diagrams, which references pin connections to V
Updated addresses for interrupt vectors 80, 81, 82 and 83-125
(see Table 7-1).
Updated the Oscillator System Diagram (see Figure 8-1).
Added Note 1 to the Oscillator Tuning register (OSCTUN) (see
Register 8-4).
Removed Table 10-1 and added reference to pin diagrams for I/O
pin availability and functionality.
Updated the UTXINV bit settings in the UxSTA register and
added Note 1 (see Register 19-2).
Updated the Min value for parameter DC12 (RAM Retention
Voltage) and added Note 4 to the DC Temperature and Voltage
Specifications (see Table 24-4).
Updated the Min value for parameter DI35 (see Table 24-20).
Updated AD08 and added reference to Note 2 for parameters
AD05a, AD06a and AD08a (see Table 24-38).
Update Description
DS70283H-page 309
SS
.
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