DSPIC33FJ32MC204-E/ML Microchip Technology, DSPIC33FJ32MC204-E/ML Datasheet - Page 218
![16-bit DSC, 32KB Flash,Motor,40 MIPS,nanoWatt 44 QFN 8x8x0.9mm TUBE](/photos/6/81/68122/150-44-qfn_sml.jpg)
DSPIC33FJ32MC204-E/ML
Manufacturer Part Number
DSPIC33FJ32MC204-E/ML
Description
16-bit DSC, 32KB Flash,Motor,40 MIPS,nanoWatt 44 QFN 8x8x0.9mm TUBE
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Datasheets
1.DSPIC33FJ32MC202-IMM.pdf
(320 pages)
2.DSPIC33FJ32MC202-IMM.pdf
(14 pages)
3.DSPIC33FJ32MC202-IMM.pdf
(14 pages)
Specifications of DSPIC33FJ32MC204-E/ML
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
35
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 9x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
44-QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- DSPIC33FJ32MC202-IMM PDF datasheet
- DSPIC33FJ32MC202-IMM PDF datasheet #2
- DSPIC33FJ32MC202-IMM PDF datasheet #3
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- Download datasheet (5Mb)
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304
21.8
The
dsPIC33FJ16MC304 devices offer the intermediate
implementation of CodeGuard™ Security. CodeGuard
Security enables multiple parties to securely share
resources (memory, interrupts and peripherals) on a
single chip. This feature helps protect individual
Intellectual Property in collaborative system designs.
TABLE 21-3:
DS70283H-page 218
BSS<2:0> = x11
BSS<2:0> = x10
BSS<2:0> = x01
BSS<2:0> = x00
CONFIG BITS
1792
256
768
0K
Code Protection and
CodeGuard™ Security
dsPIC33FJ32MC202/204
CODE FLASH SECURITY
SEGMENT SIZES FOR
32 KBYTE DEVICES
GS = 10240 IW
GS = 11008 IW
GS = 7168 IW
GS = 3072 IW
BS = 3840 IW
BS = 7936 IW
VS = 256 IW
VS = 256 IW
BS = 768 IW
VS = 256 IW
VS = 256 IW
000000h
000200h
000800h
001FFEh
002000h
003FFEh
004000h
000000h
000200h
000800h
001FFEh
002000h
003FFEh
004000h
000000h
000200h
000800h
001FFEh
002000h
003FFEh
004000h
000000h
000200h
000800h
001FFEh
002000h
003FFEh
004000h
0001FEh
0007FEh
0057FEh
0001FEh
0007FEh
0057FEh
0001FEh
0007FEh
0057FEh
0001FEh
0007FEh
0057FEh
and
When coupled with software encryption libraries, Code-
Guard™ Security can be used to securely update Flash
even when multiple IPs reside on the single chip.
The code protection features are controlled by the
Configuration registers: FBS and FGS.
Secure
implemented
dsPIC33FJ16MC304 devices.
TABLE 21-4:
BSS<2:0> = x11
BSS<2:0> = x10
BSS<2:0> = x01
BSS<2:0> = x00
Note:
CONFIG BITS
1792
256
768
0K
segment
Refer to Section 23. “CodeGuard™
Security”
“dsPIC33F/PIC24H
Manual” for further information on usage,
configuration
CodeGuard Security.
in
CODE FLASH SECURITY
SEGMENT SIZES FOR
16 KBYTE DEVICES
and
dsPIC33FJ32MC202/204
© 2011 Microchip Technology Inc.
GS = 5376 IW
GS = 4608 IW
GS = 1536 IW
BS = 3840 IW
BS = 5376 IW
VS = 256 IW
VS = 256 IW
BS = 768 IW
VS = 256 IW
VS = 256 IW
(DS70199)
RAM
and
Family
protection
operation
000000h
000200h
000800h
002000h
002BFEh
000000h
000200h
000800h
002000h
002BFEh
000000h
000200h
000800h
002000h
002BFEh
000000h
000200h
000800h
002000h
002BFEh
0001FEh
0007FEh
001FFEh
0001FEh
0007FEh
001FFEh
0001FEh
0007FEh
001FFEh
0001FEh
0007FEh
001FFEh
Reference
in
is
the
and
not
of
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