EVAL-ADF7021-NDBZ2 Analog Devices Inc, EVAL-ADF7021-NDBZ2 Datasheet - Page 52

• Manufacturer Part Number: EVAL-ADF7021-NDBZ2
• Description: 860 MHz To 870 MHz
• Manufacturer: Analog Devices Inc
• Type: Transceiver, FSKr

Specifications of EVAL-ADF7021-NDBZ2

• Frequency: 860MHz ~ 870MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: ADF7021-N
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADF7021-N
REGISTER 3—TRANSMIT/RECEIVE CLOCK REGISTER
•
•
•
Baseband offset clock frequency (BBOS CLK) must be
greater than 1 MHz and less than 2 MHz, where
Set the demodulator clock (DEMOD CLK) such that
2 MHz ≤ DEMOD CLK ≤ 15 MHz, where
For 2FSK/3FSK, the data/clock recovery frequency (CDR
CLK) needs to be within 2% of (32 × data rate). For 4FSK,
the CDR CLK needs to be within 2% of (32 × symbol rate).
GD6
0
0
...
1
DEMOD
CDR
BBOS
AGC_CLK_DIVIDE
GD5
0
0
...
1
CLK
CLK
CLK
GD4
0
0
...
1
=
=
CDR
BBOS
=
GD3
0
0
...
1
DEMOD
DEMOD
_
CLK
_
GD2
0
0
...
1
CLK
XTAL
_
CLK
_
DIVIDE
_
GD1
0
1
...
1
XTAL
CLK
DIVIDE
SEQ_CLK_DIVIDE
SK8
0
0
.
1
1
AGC_CLK_DIVIDE
INVALID
1
...
63
_
DIVIDE
Figure 66. Register 3—Transmit/Receive Clock Register Map
SK7
0
0
.
1
1
...
...
...
...
...
...
SK3
0
0
.
1
1
SK2
0
1
.
1
1
Rev. 0 | Page 52 of 64
FS8
0
0
.
1
1
SK1
1
0
.
0
1
CDR_CLK_DIVIDE
FS7
0
0
.
1
1
SEQ_CLK_DIVIDE
1
2
.
254
255
...
...
...
...
...
...
•
•
The sequencer clock (SEQ CLK) supplies the clock to the
digital receive block. It should be as close to 100 kHz as
possible.
The time allowed for each AGC step to settle is determined
by the AGC update rate. It should be set close to 8 kHz.
FS3
0
0
.
1
1
SEQ
AGC
FS2
0
1
.
1
1
CLK
Update
FS1
1
0
.
0
1
OK4
0
0
...
1
=
DEMOD_CLK_
SEQ
OK3
CDR_CLK_ DIVIDE
0
0
...
1
1
2
.
254
255
Rate
DIVIDE
_
OK2
0
0
...
1
[Hz] =
CLK
XTAL
OK1
0
1
...
1
BK2
0
0
1
1
_
DIVIDE
AGC
DEMOD_CLK_DIVIDE
INVALID
1
...
15
BK1
0
1
0
1
_
BBOS_CLK_DIVIDE
4
8
16
32
SEQ
CLK
ADDRESS
CLK
BITS
_
DIVIDE