DS33Z11 Maxim Integrated Products, DS33Z11 Datasheet - Page 162

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DS33Z11

Manufacturer Part Number
DS33Z11
Description
Network Controller & Processor ICs Ethernet Mapper Ethe rnet-Serial TDM Ethe
Manufacturer
Maxim Integrated Products
Datasheet

Specifications of DS33Z11

Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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11.13 JTAG Interface Timing
(VDD3.3 = 3.3V ±5%, VDD1.8 = 1.8 ±5%; T
Note 1: Clock can be stopped high or low.
Figure 11-14 JTAG Interface Timing Diagram
JTCLK Clock Period
JTCLK Clock High: Low Time
(Note 1)
JTCLK to JTDI, JTMS Setup
Time
JTCLK to JTDI, JTMS Hold Time
JTCLK to JTDO Delay
JTCLK to JTDO HIZ Delay
JTRST Width Low Time
JTDI, JTMS
JTRST
JTCLK
JTD0
PARAMETER
t6
t7
t2
SYMBOL
t2:t3
t1
t4
t5
t6
t7
t8
t4
j
= -40°C to +85°C.)
t1
t5
162 of 172
MIN
100
50
2
2
2
2
t3
t8
1000
TYP
500
MAX
50
50
UNITS
ns
ns
ns
ns
ns
ns
ns

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