DS33Z11 Maxim Integrated Products, DS33Z11 Datasheet - Page 21

• Manufacturer Part Number: DS33Z11
• Description: Network Controller & Processor ICs Ethernet Mapper Ethe rnet-Serial TDM Ethe
• Manufacturer: Maxim Integrated Products

Specifications of DS33Z11

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

A2/X86ED
D2/SPICK
D0/MOSI
D1/MISO
NAME
A3
A4
A5
A6
A7
A8
A9
D3
D4
D5
DS33Z11
CSBGA
PIN #
(169)
A2
B2
C2
A3
B3
C3
A4
B4
A5
A6
A7
B5
B6
B7
revision to
DS33ZH1
Potential
BGA(100)
add on
ball B4
PIN #
future
E10
E8
E9
—
—
—
—
—
—
—
—
—
—
1
TYPE
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
—
—
—
—
—
—
—
—
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Address Bit 2: Address bit 2 of the microprocessor
interface.
X86ED (Hardware Mode): When in Hardware Mode,
setting this pin high enables X.86 encapsulation for both
the transmit and receive data. When 0, HDLC
encapsulation is used. The register used to control this
function in Software Mode is LI.TX86EDE.
Address Bit 3: Address bit 3 of the microprocessor
interface.
Address Bit 4: Address bit 4 of the microprocessor
interface.
Address Bit 5: Address bit 5 of the microprocessor
interface.
Address Bit 6: Address bit 6 of the microprocessor
interface.
Address Bit 7: Address bit 7 of the microprocessor
interface.
Address Bit 8: Address bit 8 of the microprocessor
interface.
Address Bit 9: Address bit 9 of the microprocessor
interface. Most Significant Bit.
Data Bit 0: Bi-directional data bit 0 of the microprocessor
interface. Least Significant Bit. Not driven when CS = 1 or
RST = 0.
Master Out Slave In (SPI Mode): Data stream that
provides the instruction and address information to the
external EEPROM when in SPI Master Mode. MOSI is
updated on the rising edge when CKPHA is set high, and
on the falling edge when set low.
Data Bit 1: Bidirectional data bit 1 of the microprocessor
interface. Not driven when CS = 1 or RST = 0.
Master In Slave Out (SPI Mode): Data path from the SPI
EEPROM to the DS33Z11. Must be synchronous with
SPICK. The Serial EEPROM SPI Interface will provide
data to the DS33Z11, MSB first. MISO is sampled on the
falling edge when CKPHA is set high, and on the rising
edge when set low.
Data Bit 2: Bidirectional data bit 2 of the microprocessor
interface. Not driven when CS = 1 or RST = 0.
SPICK: Provides clocking for SPI transactions.
Data Bit 3: Bidirectional data bit 3 of the microprocessor
interface. Not driven when CS = 1 or RST = 0.
Data Bit 4: Bidirectional data bit 4 of the microprocessor
interface. Not driven when CS = 1 or RST = 0.
Data Bit 5: Bidirectional data bit 5 of the microprocessor
interface. Not driven when CS = 1 or RST = 0.
FUNCTION