DS33Z11 Maxim Integrated Products, DS33Z11 Datasheet - Page 166
DS33Z11
Manufacturer Part Number
DS33Z11
Description
Network Controller & Processor ICs Ethernet Mapper Ethe rnet-Serial TDM Ethe
Manufacturer
Maxim Integrated Products
Datasheet
1.DS33Z11.pdf
(172 pages)
Specifications of DS33Z11
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Figure 12-2 TAP Controller State Diagram
12.2 Instruction Register
The instruction register contains a shift register as well as a latched parallel output and is 3 bits in length. When
the TAP controller enters the Shift-IR state, the instruction shift register is connected between JTDI and JTDO.
While in the Shift-IR state, a rising edge on JTCLK with JTMS LOW will shift the data one stage towards the serial
output at JTDO. A rising edge on JTCLK in the Exit1-IR state or the Exit2-IR state with JTMS HIGH will move the
controller to the Update-IR state. The falling edge of that same JTCLK will latch the data in the instruction shift
register to the instruction parallel output. Instructions supported by the DS33Z11 and its respective operational
binary codes are shown in
1
0
Test Logic
Reset
Run Test/
Idle
0
Table
1
12-1.
0
1
Capture DR
Update DR
1
Select
DR-Scan
Pause DR
Exit2 DR
Shift DR
Exit DR
0
1
0
0
1
0
1
166 of 172
1
0
0
1
0
1
Capture IR
Update IR
1
Pause IR
Select
IR-Scan
Shift IR
Exit2 IR
Exit IR
0
1
1
1
0
0
0
1
1
0
0