DS33Z11 Maxim Integrated Products, DS33Z11 Datasheet - Page 80

• Manufacturer Part Number: DS33Z11
• Description: Network Controller & Processor ICs Ethernet Mapper Ethe rnet-Serial TDM Ethe
• Manufacturer: Maxim Integrated Products

Specifications of DS33Z11

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 3: MAC Read Pointer Reset (C1MRPR) Setting this bit to 1 resets the receive queue read pointer for
connection 1. This queue pointer must be reset after a disconnect and before a connection. The user must clear
the bit before subsequent reset operations.
Bit 2: HDLC Write Pointer Reset (C1HWPR) Setting this bit to 1 resets the receive queue write pointer for
connection 1. This queue pointer must be reset after a disconnect and before a connection. The user must clear
the bit before subsequent reset operations.
Bit 1: HDLC Read Pointer Reset (C1MHPR) Setting this bit to 1 resets the transmit queue read pointer for
connection 1. This queue pointer must be reset after a disconnect and before a connection. The user must clear
the bit before subsequent reset operations.
Bit 0: MAC Transmit Write Pointer Reset (C1HRPR) Setting this bit to 1 resets the transmit queue write pointer
for connection 1. This queue pointer must be reset after a disconnect and before a connection. The user must
clear the bit before subsequent reset operations.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 0: BIST Enable (BISTE) If this bit is set the DS33Z11 performs BIST test on the SDRAM. Normal data
communication is halted while BIST enable is high. The user must reset the DS33Z11 after completion of BIST
test before normal dataflow can begin.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 1: BIST DONE (BISTDN) If this bit is set to 1, the DS33Z11 has completed the BIST Test initiated by BISTE.
The pass fail result is available in BISTPF.
Bit 0: BIST PassFail (BISTPF) This bit is equal to 0 after the DS33Z11 performs BIST testing on the SDRAM
and the test passes. This bit is set to 1 if the test failed. This bit is valid only after the BIST test is complete and
the BIST DN bit is set. If set this bit can only be cleared by resetting the DS33Z11.
7
0
-
7
0
7
0
-
-
6
0
-
6
0
6
0
-
-
GL.C1QPR
Connection 1 Queue Pointer Reset
12h
GL.BISTEN
BIST Enable
20h
GL.BISTPF
BIST PassFail
21h
5
0
-
5
0
5
0
-
-
4
0
-
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4
0
4
0
-
-
C1MRPRR
3
0
3
0
3
0
-
-
C1HWPRR
2
0
2
0
2
0
-
-
C1MHPR
BISTDN
1
0
1
0
1
0
-
C1HRPR
BISTPF
BISTE
0
0
0
0
0
0