LAN9313I-NZW SMSC, LAN9313I-NZW Datasheet
LAN9313I-NZW
Specifications of LAN9313I-NZW
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LAN9313I-NZW Summary of contents
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... Remapping of 802.1Q priority field on per port basis – Programmable rate limiting at the ingress/egress ports with random early discard, per port / priority — IGMP v1/v2/v3 monitoring for Multicast packet filtering — Programmable filter by MAC address SMSC LAN9313/LAN9313i LAN9313/LAN9313i Three Port 10/100 Managed Ethernet Switch with MII Switch Management — ...
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... LAN9313-NU For 128-Pin, VTQFP Lead-Free RoHS Compliant Package (0 TO 70°C Temp Range) LAN9313-NZW For 128-Pin, XVTQFP Lead-Free RoHS Compliant Package (0 TO 70°C Temp Range) LAN9313i-NZW For 128-Pin, XVTQFP Lead-Free RoHS Compliant Package (-40 TO 85°C Temp Range) This product meets the halogen maximum concentration values per IEC61249-2-21 ...
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... Hard-Straps..................................................................................................................................................................................................... 50 4.3 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 4.3.1 Port 1 & 2 PHY Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Chapter 5 System Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 5.1 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 5.2 Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 5.2.1 1588 Time Stamp Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 5.2.2 Switch Fabric Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 5.2.3 Ethernet PHY Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 5.2.4 GPIO Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 SMSC LAN9313/LAN9313i 3 DATASHEET Revision 1.7 (06-29-10) ...
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... Port 1 & 2 PHYs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 7.2.1 100BASE-TX Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 7.2.1.1 MII MAC Interface ........................................................................................................................................................................................... 86 7.2.1.2 4B/5B Encoder................................................................................................................................................................................................ 86 7.2.1.3 Scrambler and PISO ....................................................................................................................................................................................... 88 7.2.1.4 NRZI and MLT-3 Encoding ............................................................................................................................................................................. 88 7.2.1.5 100M Transmit Driver ..................................................................................................................................................................................... 88 Revision 1.7 (06-29-10) Three Port 10/100 Managed Ethernet Switch with MII 4 DATASHEET Datasheet SMSC LAN9313/LAN9313i ...
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... READ (Read Location) ................................................................................................................................................................................. 111 8.2.3.7 WRITE (Write Location) ................................................................................................................................................................................ 112 8.2.3.8 WRAL (Write All)........................................................................................................................................................................................... 112 8.2.4 EEPROM Loader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 8.2.4.1 EEPROM Loader Operation ......................................................................................................................................................................... 113 8.2.4.2 EEPROM Valid Flag ..................................................................................................................................................................................... 115 8.2.4.3 MAC Address................................................................................................................................................................................................ 115 8.2.4.4 Soft-Straps .................................................................................................................................................................................................... 115 SMSC LAN9313/LAN9313i 5 DATASHEET Revision 1.7 (06-29-10) ...
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... GPIO IEEE 1588 Timestamping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 12.2.1.1 IEEE 1588 GPIO Inputs ................................................................................................................................................................................ 143 12.2.1.2 IEEE 1588 GPIO Outputs ............................................................................................................................................................................. 143 12.2.2 GPIO Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 12.2.2.1 GPIO Interrupt Polarity.................................................................................................................................................................................. 143 Revision 1.7 (06-29-10) Three Port 10/100 Managed Ethernet Switch with MII 6 DATASHEET Datasheet SMSC LAN9313/LAN9313i ...
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... Free Running 25MHz Counter Register (FREE_RUN)................................................................................................................................. 229 13.1.8.7 Reset Control Register (RESET_CTL) ......................................................................................................................................................... 230 13.2 Ethernet PHY Control and Status Registers 231 13.2.1 Virtual PHY Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 13.2.2 Port 1 & 2 PHY Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 13.2.2.1 Port x PHY Basic Control Register (PHY_BASIC_CONTROL_x) ................................................................................................................ 233 SMSC LAN9313/LAN9313i 7 DATASHEET Revision 1.7 (06-29-10) ...
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... Switch Engine DIFFSERV Table Read Data Register (SWE_DIFFSERV_TBL_RD_DATA) ....................................................................... 327 13.3.3.15 Switch Engine DIFFSERV Table Command Status Register (SWE_DIFFSERV_TBL_CMD_STS) ............................................................ 328 13.3.3.16 Switch Engine Global Ingress Configuration Register (SWE_GLOBAL_INGRSS_CFG)............................................................................. 329 Revision 1.7 (06-29-10) Three Port 10/100 Managed Ethernet Switch with MII 8 DATASHEET Datasheet SMSC LAN9313/LAN9313i ...
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... Power-On Configuration Strap Valid Timing 390 14.5.4 Microwire Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391 14.5.5 SPI Slave Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392 14.6 Clock Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393 Chapter 15 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394 15.1 128-VTQFP Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394 15.2 128-XVTQFP Package Outline 396 Chapter 16 Datasheet Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398 SMSC LAN9313/LAN9313i 9 DATASHEET Revision 1.7 (06-29-10) ...
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... Figure 9.6 MII Mux Management Path Connections - PHY Mode I2C/SPI Managed . . . . . . . . . . . . . . 133 Figure 10.1 IEEE 1588 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 Figure 10.2 IEEE 1588 Message Time Stamp Point 136 Figure 13.1 LAN9313/LAN9313i Base Register Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 Figure 13.2 Example SWITCH_MAC_ADDRL, SWITCH_MAC_ADDRH, and EEPROM Setup . . . . . . 203 Figure 14.1 Output Equivalent Test Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388 Figure 14 ...
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... Three Port 10/100 Managed Ethernet Switch with MII Datasheet Figure 15.1 LAN9313 128-VTQFP Package Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394 Figure 15.2 LAN9313 128-VTQFP Recommended PCB Land Pattern 395 Figure 15.3 LAN9313/LAN9313i 128-XVTQFP Package Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396 Figure 15.4 LAN9313/LAN9313i 128-XVTQFP Recommended PCB Land Pattern . . . . . . . . . . . . . . . . 397 SMSC LAN9313/LAN9313i 11 DATASHEET Revision 1 ...
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... Table 3.9 PLL Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Table 3.10 Core and I/O Power and Ground Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Table 3.11 No-Connect Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Table 4.1 Reset Sources and Affected LAN9313/LAN9313i Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Table 4.2 Soft-Strap Configuration Strap Definitions Table 4.3 Hard-Strap Configuration Strap Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Table 6.1 Switch Fabric Flow Control Enable Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Table 6 ...
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... Table 14.7 Power-On Configuration Strap Latching Timing Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390 Table 14.8 Microwire Timing Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391 Table 14.9 SPI Slave Timing Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392 Table 14.10LAN9313/LAN9313i Crystal Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393 Table 15.1 LAN9313 128-VTQFP Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394 Table 15.2 LAN9313/LAN9313i 128-XVTQFP Dimensions 397 Table 16.1 Customer Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398 SMSC LAN9313/LAN9313i 13 DATASHEET ...
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... External system (Includes processor, application software, etc.) Internet Group Management Protocol Refers to data input to the LAN9313/LAN9313i from the host This type of status bit is set whenever the condition that it represents is asserted. The bit remains set until the condition is no longer true, and the status bit is cleared by writing a zero ...
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... Not Applicable No Connect Organizationally Unique Identifier Refers to data output from the LAN9313/LAN9313i to the host Program I/O cycle. An SRAM-like read or write cycle on the HBI. Parallel In Serial Out Phase Locked Loop Precision Time Protocol Refers to a reserved bit field or address ...
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... Unless otherwise noted in the pin description, internal pull-downs are always enabled. Note: Internal pull-down resistors prevent unconnected inputs from floating. Do not rely on internal resistors to drive signals external to the LAN9313/LAN9313i. When connected to a load that must be pulled low, an external resistor must be added. AI Analog input ...
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... Many of these register bit notations can be combined. Some examples of this are shown below: R/W: Can be written. Will return current setting on a read. R/WAC: Will return current setting on a read. Writing anything clears the bit. SMSC LAN9313/LAN9313i Table 1.2 Register Bit Types REGISTER BIT DESCRIPTION ...
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... MACs and PHYs support full/half duplex 10BASE-T and 100BASE-TX operation. The LAN9313/LAN9313i provides 2 on-chip PHYs, 1 Virtual PHY and 3 MACs. The Virtual PHY and the third MAC are used to connect the LAN9313/LAN9313i switch fabric to an external MAC or PHY. All ports support automatic or manual full duplex flow control or half duplex backpressure (forced collision) flow control ...
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... System GP Timer IEEE 1588 System Clocks/ Interrupt Reset/PME Controller Free-Run Controller Clk IRQ External 25MHz Crystal Figure 2.1 Internal LAN9313/LAN9313i Block Diagram Virtual PHY Registers MDIO MDIO To optional PHY, MAC, MII MII MII or SMI Master Mode MUX PHY Management MDIO Management Mode ...
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... Pin Reset A multi-module reset is initiated by assertion of the following: Digital Reset - DIGITAL_RST (bit 0) in the - Resets all LAN9313/LAN9313i sub-modules except the Ethernet PHYs (Port 1 PHY, Port 2 PHY, and Virtual PHY) A single-module reset is initiated by assertion of the following: Port 2 PHY Reset - PHY2_RST (bit 2) in the ...
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... Ethernet PHYs The LAN9313/LAN9313i contains three PHYs: Port 1 PHY, Port 2 PHY and a Virtual PHY. The Port 1 & 2 PHYs are identical in functionality and each connect their corresponding Ethernet signal pins to the switch fabric MAC of their respective port. These PHYs interface with their respective MAC via an internal MII interface ...
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... This module provides a SMI slave interface which can be used for CPU management of the LAN9313/LAN9313i via the MII pins, and allows CPU access to all system CSRs. SMI uses the same pins and protocol of the IEEE MII management function, and differs only in that SMI provides access to all internal registers by using a non-standard extended addressing map ...
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... MAC Mode The LAN9313/LAN9313i MAC mode utilizes an external PHY, which is connected to the MII pins, to provide a third Ethernet network connection. In this mode, the LAN9313/LAN9313i acts as a MAC, providing a communication path between the switch fabric and the external PHY. In MAC mode, the LAN9313/LAN9313i may be unmanaged, SMI managed, I Section 2.3.3, " ...
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... EEPROM and for CPU R/W access to EEPROM PHY Mode Used to load initial SPI Managed configuration from EEPROM and for CPU R/W access to EEPROM Revision 1.7 (06-29-10) Table 2.1 LAN9313/LAN9313i Modes 2 I C/SPI SLAVE SMI/MIIM INTERFACE INTERFACE Not used Not used Not used ...
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... Magnetics Microwire EEPROM (optional) To Ethernet Magnetics To Ethernet Magnetics To Ethernet Microwire Magnetics EEPROM (optional Ethernet I C Magnetics To Ethernet Microprocessor/ Magnetics Microcontroller LAN9313/LAN9313i PHY Modes To Ethernet Magnetics Microwire EEPROM (optional) To Ethernet Magnetics To Ethernet Microwire Magnetics EEPROM (optional Ethernet I C Magnetics Microprocessor/ Microcontroller 25 DATASHEET ...
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... Three Port 10/100 Managed Ethernet Switch with MII SMSC LAN9313 128-VTQFP TOP VIEW 26 DATASHEET Datasheet 64 VDD33IO 63 IRQ 62 TXER 61 RXD0 60 MII_DUPLEX AUTO_MDIX_1 55 AUTO_NEG_1 54 VDD33IO 53 SPEED_1 52 DUPLEX_1 51 BP_EN_1 50 FD_FC_1 49 MANUAL_FC_1 48 VSS 47 LED_FUN0 46 VDD33IO 45 LED_FUN1 44 LED_EN 43 AUTO_MDIX_2 42 AUTO_NEG_2 41 SPEED_2 40 VDD18CORE 39 VDD33IO 38 DUPLEX_2 37 BP_EN_2 36 FD_FC_2 35 MANUAL_FC_2 SPEED_MII 34 VDD33IO 33 SMSC LAN9313/LAN9313i ...
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... RXP2 123 RXN2 124 VDD33A2 125 TXP2 126 TXN2 127 VSS 128 Figure 3.2 LAN9313/LAN9313i 128-XVTQFP Pin Assignments (TOP VIEW) SMSC LAN9313/LAN9313i SMSC LAN9313/LAN9313i 128-XVTQFP TOP VIEW VSS NOTE: EXPOSED PAD ON BOTTOM OF PACKAGE MUST BE CONNECTED TO GROUND 27 DATASHEET VDD33IO 64 63 IRQ ...
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... Pin Descriptions This section contains the descriptions of the LAN9313/LAN9313i pins. The pin descriptions have been broken into functional groups as follows: LAN Port 1 Pins LAN Port 2 Pins LAN Port 1 & 2 Power and Common Pins LAN Port 0(External MII) Pins Dedicated Configuration Strap Pins ...
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... EXRES AI Bias Reference: Used for internal bias circuits. Connect to an external 12.4K ohm, 1% resistor to ground. VDD33A1 P +3.3V Port 1 Analog Power Supply Refer to the LAN9313/LAN9313i application note for additional connection information. 29 DATASHEET DESCRIPTION (LED_CFG), LED Configuration Register General Purpose I/O Configuration and General Purpose I/O (GPIO_DATA_DIR) ...
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... MII Transmit Data: The functionality of these signals is dependant on the mode of the (PD) LAN9313/LAN9313i: Note 3.3 In MAC mode, this is the data from the LAN9313/LAN9313i switch to an external PHY. See Note In PHY mode, this is the data from an external MAC to the LAN9313/LAN9313i switch. TXEN IS/O8 MII Transmit Enable: Indicates valid data on TXD[3:0] ...
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... MAC. See RXD[3:0] IS/O8 MII Receive Data: (PD) Note 3.3 In MAC mode, this is the data from an external PHY to the LAN9313/LAN9313i switch. In PHY mode, this is the data from the LAN9313/LAN9313i switch to an external MAC. See Note 31 DATASHEET DESCRIPTION Note 3.3. Note 3 ...
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... MII_DULPEX value of 0 indicates full duplex, and 1 indicates half duplex. If duplex_pol_strap_mii MII_DULPEX value of 1 indicates full duplex, and 0 indicates half duplex. 32 DATASHEET Three Port 10/100 Managed Ethernet Switch with MII Datasheet DESCRIPTION Note 3.3. Note 3.3. 3.6. bit in the Virtual PHY SMSC LAN9313/LAN9313i of ...
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... Select Strap 53 Port 1 Duplex DUPLEX_1 Select Strap 52 Port 1 BP_EN_1 Backpressure Enable Strap 51 SMSC LAN9313/LAN9313i BUFFER TYPE LED_EN IS LED Enable Strap: Configures the default value for the LED_EN bits in the (PU) Register Note 3.8 LED/GPIO pins are configured as GPIOs. When latched high, all 8 LED/GPIO pins are configured as LEDs ...
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... When latched high, backpressure is enabled. See 34 DATASHEET Datasheet Port 1 Full- Port 1 Manual Flow Port 1 Full- Port 1 Manual Flow Port 1 Full-Duplex Receive bits. See Auto- enable bit in the Note 3.9. bit in the Port 2 Backpressure Port 2 Manual Flow Note 3.9. SMSC LAN9313/LAN9313i ...
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... DUPLEX_POL_MII (External MII) Duplex Polarity Strap 32 Port 0 BP_EN_MII (External MII) Backpressure Enable Strap 31 SMSC LAN9313/LAN9313i BUFFER TYPE DESCRIPTION IS Port 2 Full-Duplex Flow Control Enable Strap: Configures the default value of the (PU) Duplex Transmit Flow Control Enable (TX_FC_2) Note 3.8 and Port 2 Full-Duplex Receive Flow Control ...
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... PHYs (Virtual, (PU) Port 1, and Port 2) as detailed in Note 3.8 "PHY Addressing," on page See Note 3.9. Section 4.2.4, "Configuration Straps," DATASHEET Datasheet Port Note 3.9. Port 0(External MII) (MANUAL_FC_MII). Port 0(External MII) Manual (MANUAL_FC_MII). See Section 7.1.1, 84 SMSC LAN9313/LAN9313i ...
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... EEPROM Microwire Serial Clock 2 EEPROM I C Serial Clock 99 EEPROM EEPROM_SIZE_1 Size Strap 1 SMSC LAN9313/LAN9313i for more information. Table 3.6 EEPROM Pins BUFFER SYMBOL TYPE EEDI IS EEPROM Microwire Data Input (EEDI): In Microwire EEPROM mode (EEPROM_TYPE = 0), (PD) this pin is the Microwire EEPROM serial data input. ...
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... IS SPI Slave Chip Select: SPI slave mode chip select input. When low, the LAN9313/LAN9313i (PU) SPI slave is selected for SPI transfers. When high, the SPI serial data output (SO) is 3-stated slave, SMI slave, and unmanaged modes, this pin is not used ...
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... IS System Reset Input: This active low signal allows external hardware to reset the LAN9313/LAN9313i. (PU) The LAN9313/LAN9313i also contains an internal power-on reset circuit. Thus, this signal may be left unconnected if an external hardware reset is not needed. When used, this signal must adhere to the reset timing requirements as detailed in 14.5.2, " ...
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... P Digital Core +1.8V Power Supply Output: +1.8V power from the internal core voltage regulator. All VDD18CORE pins must be tied together for proper operation. Refer to the LAN9313/LAN9313i application note for additional connection information. VSS P Common Ground Table 3.11 No-Connect Pins ...
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... Resets The LAN9313/LAN9313i provides multiple hardware and software reset sources, which allow varying levels of the LAN9313/LAN9313i to be reset. All resets can be categorized into three reset types as described in the following sections: Chip-Level Resets —Power-On Reset (POR) —nRST Pin Reset Multi-Module Resets — ...
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... Power-On Reset (POR) A power-on reset occurs whenever power is initially applied to the LAN9313/LAN9313i the power is removed and reapplied to the LAN9313/LAN9313i. This event resets all circuitry within the device. Configuration straps are latched, and the EEPROM Loader is run as a result of this reset. ...
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... Digital Reset (DIGITAL_RST) A digital reset is performed by setting the DIGITAL_RST bit of the (RESET_CTL). A digital reset will reset all LAN9313/LAN9313i sub-modules except the Ethernet PHYs (Port 1 PHY, Port 2 PHY, and Virtual PHY). The EEPROM Loader will automatically run following this reset. Configuration straps are not latched as a result of a digital reset. ...
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... Reset bit in the Upon completion of the Port 2 PHY reset, the PHY2_RST and Reset bits are automatically cleared. No other modules of the LAN9313/LAN9313i are affected by this reset. In addition to the methods above, the Port 2 PHY is automatically reset after returning from a PHY power-down mode. This reset differs in that the PHY power-down mode reset does not reload or reset any of the PHY registers ...
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... Datasheet 4.2.4 Configuration Straps Configuration straps allow various features of the LAN9313/LAN9313i to be automatically configured to user defined values. Configuration straps can be organized into two main categories: hard-straps and soft-straps. Both hard-straps and soft-straps are latched upon Power-On Reset (POR) or pin reset (nRST). The primary difference between these strap types is that soft-strap default values can be overridden by the EEPROM Loader, while hard-straps cannot ...
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... When configured low, auto-negotiation is Port x PHY Auto-Negotiation Port x PHY Special Modes Register Speed Select LSB (PHY_SPEED_SEL_LSB) Section Port x PHY Basic Port x PHY Auto-Negotiation Port x PHY Special Modes Register 46 DATASHEET Datasheet PIN / DEFAULT VALUE AUTO_MDIX_1 is cleared cleared. AUTO_NEG_1 enable bit SPEED_1 bit in 13.2.2.1). SMSC LAN9313/LAN9313i ...
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... Port 2 Manual MDIX Strap: Configures MDI(0) or MDIX(1) for Port 2 when the auto_mdix_strap_2 is low and the AMDIXCTL bit of the Indication Register (PHY_SPECIAL_CONTROL_STAT_IND_x) SMSC LAN9313/LAN9313i Duplex Mode (PHY_DUPLEX) bit in the Section Port x PHY Basic Control Port x PHY Auto- Port x PHY Special Modes Register ...
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... Port x PHY Auto-Negotiation Port x PHY Special Modes Register Duplex Mode (PHY_DUPLEX) bit in the Section Port x PHY Basic Control Port x PHY Auto- Port x PHY Special Modes Register 48 DATASHEET Datasheet PIN / DEFAULT VALUE AUTO_NEG_2 enable bit SPEED_2 bit in 13.2.2.1). DUPLEX_2 13.2.2.1). SMSC LAN9313/LAN9313i ...
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... Port 0(External MII) Backpressure Enable Strap: Configures the default value for the Enable (BP_EN_MII) Flow Control Register configured low, backpressure is disabled. When configured high, backpressure is enabled. SMSC LAN9313/LAN9313i Port 2 Backpressure Enable bit of the Port 2 Manual Flow Control Register Port 2 Full-Duplex and ...
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... DESCRIPTION 2 C Managed Mode Section 2.3, "Modes of Operation," on page Mode 50 DATASHEET Three Port 10/100 Managed Ethernet Switch with MII Datasheet PIN / DEFAULT VALUE FD_FC_MII MANUAL_FC_MII 0b Virtual PHY Table 4.3 provides a list of 26. PIN MNGT_MODE[1:0] for EEPROM_TYPE SMSC LAN9313/LAN9313i ...
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... PHYs and Virtual PHY as detailed in 4.3 Power Management The LAN9313/LAN9313i Port 1 and Port 2 PHYs support several power management and wakeup features. 4.3.1 Port 1 & 2 PHY Power Management The Port 1 & 2 PHYs provide independent general power-down and energy-detect power-down modes which reduce PHY power consumption ...
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... LAN9313/LAN9313i provides a multi-tier programmable interrupt structure which is controlled by the System Interrupt Controller. The programmable system interrupts are generated internally by the various LAN9313/LAN9313i sub-modules and can be configured to generate a single external host interrupt via the IRQ interrupt output pin. The programmable nature of the host interrupt provides the user with the ability to optimize performance dependent upon the application requirements ...
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... INT_STS register Bit 27 (PHY_INT2) of INT_STS register Bit 26 (PHY_INT1) of INT_STS register Bit 12 (GPIO) of INT_STS register Figure 5.1 Functional Interrupt Register Hierarchy SMSC LAN9313/LAN9313i 1588 Time Stamp Interrupt Register 1588_INT_STS_EN Switch Fabric Interrupt Registers SW_IMR SW_IPR Buffer Manager Interrupt Registers Bit 6 (BM) BM_IMR ...
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... The following sections detail each category of interrupts and their related registers. Refer to Chapter 13, "Register Descriptions," on page 146 5.2.1 1588 Time Stamp Interrupts Multiple 1588 Time Stamp interrupt sources are provided by the LAN9313/LAN9313i. The top-level 1588_EVNT (bit 29) of the event occurred in the The 1588 Interrupt Status and Enable Register (1588_INT_STS_EN) status of all 1588 interrupt conditions ...
Page 55
... For additional details on the Ethernet PHY interrupts, refer to page 96. 5.2.4 GPIO Interrupts Each GPIO[11:0] of the LAN9313/LAN9313i is provided with its own interrupt. The top-level GPIO (bit 12) of the Interrupt Status Register (INT_STS) in the General Purpose I/O Interrupt Status and Enable Register Purpose I/O Interrupt Status and Enable Register (GPIO_INT_STS_EN) and status of each GPIO[11:0] interrupt ...
Page 56
... A device ready interrupt is provided in the top-level Enable Register (INT_EN). The READY interrupt (bit 30) of the indicates that the LAN9313/LAN9313i is ready to be accessed after a power-up or reset condition. Writing this bit in the In order for a device ready interrupt event to trigger the external IRQ interrupt pin, bit 30 of the ...
Page 57
... Functional Overview At the core of the LAN9313/LAN9313i is the high performance, high efficiency 3 port Ethernet switch fabric. The switch fabric contains a 3 port VLAN layer 2 switch engine that supports untagged, VLAN tagged, and priority tagged frames. The switch fabric provides an extensive feature set which includes ...
Page 58
... Switch Fabric CSR Interface Direct Data Register address range as detailed in 58 DATASHEET Three Port 10/100 Managed Ethernet Switch with MII Datasheet for writing sequential register Switch Fabric address range automatically set Switch Fabric address range, a sub-set of the Table 13.3, “Switch Fabric CSR to 204. SMSC LAN9313/LAN9313i ...
Page 59
... The user should clear the AUTO_INC and AUTO_DEC bits before reading the last data to avoid an unintended read cycle. Figure 6.2 illustrates the process required to perform a switch fabric CSR read. SMSC LAN9313/LAN9313i CSR Write Auto Increment / Decrement Idle ...
Page 60
... Yes Write Command Register Read Data Register (MANUAL_FC_MII)). Table 6.1 60 DATASHEET Three Port 10/100 Managed Ethernet Switch with MII Datasheet CSR_BUSY = 1 Read Data No Register (Port 1 Manual Flow Control Register (MANUAL_FC_2), or Port 0(External MII) details the switch fabric flow control SMSC LAN9313/LAN9313i ...
Page 61
... Advertisement Register (VPHY_AN_ADV) Base Page Ability Register "Virtual PHY Auto-Negotiation," on page 98 SMSC LAN9313/LAN9313i Port x PHY Auto-Negotiation Advertisement Register an d Virtual PHY egotia tio n Advertisement Register are not affected by the values of the manual flow control register. Refer to ...
Page 62
... Flow Control packet will be loaded into the pause counter. The pause function is enabled by either Auto-negotiation, or manually as discussed in Revision 1.7 (06-29-10) Three Port 10/100 Managed Ethernet Switch with MII 62 DATASHEET Datasheet Section 6.2.3, SMSC LAN9313/LAN9313i ...
Page 63
... Total alignment errors Total bytes received from all packets Total bytes received from good packets Total packets with a symbol error Total MAC control packets SMSC LAN9313/LAN9313i 60. Pause frames are consumed by the MAC and not sent to (MAC_RX_CFG_x). (Section 13.3.2.3, on page 270) (Section 13.3.2.4, on page (Section 13 ...
Page 64
... DATASHEET Three Port 10/100 Managed Ethernet Switch with MII Datasheet Port x MAC Table 13.12, “Indirectly and Section 13.3.2.25 through 295) 296) 297) 298) 299) 300) 302) SMSC LAN9313/LAN9313i ...
Page 65
... Bit Age / Valid Static Filter Override SMSC LAN9313/LAN9313i (Section 13.3.2.37, on page 304) (Section 13.3.2.38, on page (Section 13.3.2.39, on page (Section 13.3.2.40, on page (Section 13.3.2.41, on page (Section 13.3.2.42, on page 309) Switch Engine ALR Write Data 0 Register and Switch Engine ALR Write Data 1 Register (SWE_ALR_WR_DAT_1) ...
Page 66
... Engine ALR Write Data 0 Register Register (SWE_ALR_WR_DAT_1). Revision 1.7 (06-29-10) Three Port 10/100 Managed Ethernet Switch with MII (SWE_PORT_INGRSS_CFG). for additional details Switch Engine ALR Command Register (SWE_ALR_WR_DAT_0), and 66 DATASHEET Datasheet Switch Engine Port (SWE_ALR_CMD_STS), Switch Switch Engine ALR Write Data 1 SMSC LAN9313/LAN9313i ...
Page 67
... Switch Engine ALR Command Register (SWE_ALR_CMD) Next Entry bit step 3. Note: Refer to Section 13.3.3.1, on page 312 definitions of these registers. SMSC LAN9313/LAN9313i with the desired MAC address and control Switch Engine ALR Command Status Register until it is cleared. Switch Engine ALR Command Register (SWE_ALR_RD_DAT_0), and Switch Engine ALR Read Data 1 Register until either are set ...
Page 68
... Enable Membership Checking is set. A NULL membership will also result in the packet being filtered if the destination address is not found in the ALR table (since the packet would have no destinations). Revision 1.7 (06-29-10 effect effect). 68 DATASHEET Three Port 10/100 Managed Ethernet Switch with MII Datasheet Spanning Tree Spanning Tree SMSC LAN9313/LAN9313i ...
Page 69
... Source Port port default table programmable Priority 3b VLAN Priority Regeneration table per port 2b ALR Priority Figure 6.4 Switch Engine Transmit Queue Selection SMSC LAN9313/LAN9313i ALR Static Bit 3b DA Highest Priority programmable priority Traffic Class 3b calculation table 3b 69 DATASHEET Figure 6.4, the priority may ...
Page 70
... Traffic Class[Resolved Priority] Get Queue Done 70 DATASHEET Three Port 10/100 Managed Ethernet Switch with MII Datasheet Get Queue Highest N Priority Y ALR Static Bit N VL Higher Priority Y Y Packet is Tagged N & Use Packet is Tagged N Resolved Priority = Priority Regen[VLAN Port] Priority] Queue = SMSC LAN9313/LAN9313i ...
Page 71
... VLAN Priority Regeneration Table Register 2 Ingress VLAN Priority Regeneration Table Register Section 13.3.3.33, on page 347 these registers. SMSC LAN9313/LAN9313i 6.5, the default priority is based on the ingress ports priority bits in its port VID Switch Engine VLAN Write Data Register (SWE_VLAN_RD_DATA), and Section 13.3.3.8, on page 321 for detailed VLAN register descriptions ...
Page 72
... Note: There is no hardware distinction between the Blocking and Disabled states. 72 DATASHEET Three Port 10/100 Managed Ethernet Switch with MII Datasheet ... 11 0 VID for detailed VLAN (Section (Section 6.4.10, on page 77). is used to place a port into one of the Software Action SMSC LAN9313/LAN9313i ...
Page 73
... Ingress Flow Metering and Coloring The LAN9313/LAN9313i supports hardware ingress rate limiting by metering packet streams and marking packets as either Green, Yellow, or Red according to three traffic parameters: Committed Information Rate (CIR), Committed Burst Size (CBS), and Excess Burst Size (EBS). A packet is marked Green if it does not exceed the CBS, Yellow if it exceeds to CBS but not the EBS, or Red otherwise ...
Page 74
... DATASHEET Three Port 10/100 Managed Ethernet Switch with MII Datasheet Bandwidth 100 Mbps 80 Mbps 67 Mbps 57 Mbps 50 Mbps 40 Mbps 31 Mbps 20 Mbps 10 Mbps 5 Mbps 2.5 Mbps 1 Mbps 500 Kbps 250 Kbps 100 Kbps 50 Kbps for detailed register SMSC LAN9313/LAN9313i ...
Page 75
... The ingress flow calculation is based on the packet type and the device configuration as shown in Figure 6.8. Y Use Precedence Flow Priority = IP Precedence Figure 6.8 Switch Engine Ingress Flow Priority Calculation SMSC LAN9313/LAN9313i Packet is IPv 4 Packet is IP Use Precedence Use IP VLAN Enable Programmable 3b DIFFSERV Table ...
Page 76
... Broadcast Storm Control In addition to ingress rate limiting, the LAN9313/LAN9313i supports hardware broadcast storm control on a per port basis. This feature is enabled via the (SWE_BCST_THROT). The allowed rate per port is specified as the number of bytes multiplied by 64 allowed to be received every 1.72 mS interval. Packets that exceed this limit are dropped. Typical ...
Page 77
... VLAN. 6.4.9 Port Mirroring The LAN9313/LAN9313i supports port mirroring where packets received or transmitted on a port or ports can also be copied onto another “sniffer” port. Port mirroring is configured using the Multiple mirrored ports can be defined, but only one sniffer port can be defined. ...
Page 78
... The flow control and drop limit thresholds are dynamic and adapt based on the current buffer usage. Based on the number of Revision 1.7 (06-29-10) Three Port 10/100 Managed Ethernet Switch with MII of Port 0 should be set. 78 DATASHEET Datasheet Port x MAC Receive configures the switch to SMSC LAN9313/LAN9313i ...
Page 79
... If any egress queue receives packets faster than the specified egress rate, packets will be accumulated in the packet memory. After the memory is used, packet dropping or flow control will be triggered. SMSC LAN9313/LAN9313i Buffer Manager Drop Level Register Buffer Manager Broadcast Buffer Level Register Section 6.4.6, " ...
Page 80
... Mbps 80 Mbps 65 Mbps 67 Mbps 56 Mbps 57 Mbps 49 Mbps 50 Mbps 39 Mbps 40 Mbps 30 Mbps 31 Mbps 20 Mbps 20 Mbps 10 Mbps 10 Mbps 5 Mbps 5 Mbps 2.5 Mbps 2.5 Mbps 990 Kbps 1 Mbps 490 Kbps 500 Kbps 250 Kbps 250 Kbps 98 Kbps 100 Kbps 49 Kbps 50 Kbps SMSC LAN9313/LAN9313i ...
Page 81
... Priority field of the new VLAN is changed to the egress ports default priority. When a packet is received special-tagged from a CPU port, the special tag is removed. SMSC LAN9313/LAN9313i Section 6.4.10, "Host CPU Port Special Tagging," on page Buffer Manager Egress Port Type Register must be set ...
Page 82
... Priority = Default Priority Priority = Unchanged [ingress_port Change Priority Y N [egress_port] Modify Tag VID = Unchanged Priority = Default Priority Send Packet Untouched [egress_port] 82 DATASHEET Three Port 10/100 Managed Ethernet Switch with MII Datasheet Special Tagged Strip Tag Strip Tag Strip Tag SMSC LAN9313/LAN9313i ...
Page 83
... Buffer Manager Port 2 Ingress Rate Drop Count Register (BM_RATE_DRP_CNT_SRC_2) 6.6 Switch Fabric Interrupts The switch fabric is capable of generating multiple maskable interrupts from the buffer manager, switch engine, and MACs. These interrupts are detailed in page 54. SMSC LAN9313/LAN9313i Section 5.2.2, "Switch Fabric Interrupts," DATASHEET Revision 1.7 (06-29-10) ...
Page 84
... Functional Overview The LAN9313/LAN9313i contains three PHYs: Port 1 PHY, Port 2 PHY and a Virtual PHY. The Port 1 & 2 PHYs are identical in functionality and each connect their corresponding Ethernet signal pins to the switch fabric MAC of their respective port. These PHYs interface with their respective MAC via an internal MII interface ...
Page 85
... Negotiation MII MII To Port x MAC Switch Fabric MAC Interface PHY Management MDIO Control To MII Mux Registers Interrupts To System Interrupt Controller SMSC LAN9313/LAN9313i and 100BASE-TX Receive and 10BASE-T Receive 10/100 Transmitter HP Auto-MDIX 10/100 Reciever LEDs PLL To GPIO/LED From Controller System Clocks Controller Figure 7 ...
Page 86
... Shaded blocks are those which are 100M PLL MII MAC 4B/5B 25MHz Interface by 4 bits Encoder 125 Mbps Serial 100M MLT-3 MLT-3 TX Driver MLT-3 CAT-5 Section 7.2.7, "MII MAC 86 DATASHEET Datasheet Scrambler 25MHz by 5 bits and PISO Magnetics Interface". Table 7.2. Each 4-bit data-nibble SMSC LAN9313/LAN9313i ...
Page 87
... MII Receive Data Valid (RXDV) 00000 /V/ INVALID, MII Receive Error (RXER) if during MII Receive Data Valid (RXDV) 00001 /V/ INVALID, MII Receive Error (RXER) if during MII Receive Data Valid (RXDV) SMSC LAN9313/LAN9313i Table 7.2 4B/5B Code Table RECEIVER INTERPRETATION 0000 DATA 0001 0010 0011 ...
Page 88
... The 100M PLL locks onto the reference clock and generates the 125MHz clock used to drive the 125 MHz logic and the 100BASE-TX Transmitter. Revision 1.7 (06-29-10) Table 7.2 4B/5B Code Table (continued) RECEIVER INTERPRETATION 88 DATASHEET Three Port 10/100 Managed Ethernet Switch with MII Datasheet TRANSMITTER INTERPRETATION INVALID INVALID INVALID INVALID INVALID INVALID Section 7.1.1, "PHY SMSC LAN9313/LAN9313i ...
Page 89
... The 100M PLL generates multiple phases of the 125MHz clock. A multiplexer, controlled by the timing unit of the DSP, selects the optimum phase for sampling the data. This is used as the received recovered clock. This clock is used to extract the serial data from the received signal. SMSC LAN9313/LAN9313i Figure 7.3. Shaded blocks are those which are internal ...
Page 90
... MII to the switch fabric MAC. The MII MAC Interface is described in detail in Interface". Note: The PHY is connected to the switch fabric MAC via standard MII signals. Refer to the IEEE 802.3 specification for additional details. Revision 1.7 (06-29-10) Three Port 10/100 Managed Ethernet Switch with MII 90 DATASHEET Datasheet Section 7.2.7, "MII MAC SMSC LAN9313/LAN9313i ...
Page 91
... The polarity of the signal is also checked. If the polarity is reversed (local RXP is connected to RXN of the remote partner and vice versa), then this is identified and corrected. The reversed condition is indicated by the flag “XPOL“, bit 4 in SMSC LAN9313/LAN9313i Section 7.2.7, "MII MAC Port x PHY Special Control/Status Indication Register ...
Page 92
... Besides the connection speed, the PHY can advertise remote fault indication and symmetric or asymmetric pause flow control as defined in the IEEE 802.3 specification. The LAN9313/LAN9313i does not support “Next Page” capability. Many of the default advertised capabilities of the PHY are determined via configuration straps as shown in PHY Auto-Negotiation Advertisement Register (PHY_AN_ADV_x)," ...
Page 93
... Advertisement Register (PHY_AN_ADV_x) x PHY Basic Control Register will be advertised. Auto-negotiation can also be disabled via software by clearing bit 12 of the PHY Basic Control Register SMSC LAN9313/LAN9313i Reset Control Register (RESET_CTL), or bit 15 of the (Section 7.2.9, "PHY Power-Down Modes," on page Port x PHY Basic Status Register (PHY_BASIC_STATUS_x) ...
Page 94
... Parallel Detection If the LAN9313/LAN9313i is connected to a device lacking the ability to auto-negotiate (i.e. no FLPs are detected able to determine the speed of the link based on either 100M MLT-3 symbols or 10M Normal Link Pulses. In this case the link is presumed to be half-duplex per the IEEE 802.3 standard. This ability is known as “ ...
Page 95
... The MII MAC Interface is responsible for the transmission and reception of the Ethernet data to and from the switch fabric MAC. The PHY is connected internally to the switch fabric MAC via standard MII signals per IEEE 802.3. SMSC LAN9313/LAN9313i Figure 7.4 (PHY_SPECIAL_CONTROL_STAT_IND_x). When AMDIXCTRL is Section 3.2, " ...
Page 96
... PHY Power-Down Modes There are two power-down modes for the PHY: PHY General Power-Down PHY Energy Detect Power-Down Note: For more information on the various power management features of the LAN9313/LAN9313i, refer to Section 4.3, "Power Management," on page Revision 1.7 (06-29-10) Three Port 10/100 Managed Ethernet Switch with MII ...
Page 97
... In addition to the chip-level hardware reset (nRST) and Power-On Reset (POR), the PHY supports three block specific resets. These are discussed in the following sections. For detailed information on all LAN9313/LAN9313i resets and the reset sequence refer to Note: The DIGITAL_RST bit in the Only a hardware reset (nRST EEPROM RELOAD command will automatically reload the configuration strap values into the PHY registers ...
Page 98
... PHY. This functionality is designed to allow easy and quick integration of the LAN9313/LAN9313i into designs with minimal driver modifications. The Virtual PHY provides a full bank of registers which comply with the IEEE 802.3 specification. This enables the Virtual PHY to provide various status and control bits similar to those provided by a real PHY ...
Page 99
... Pause) and 11 (Asymmetric Pause) of the Virtual PHY Auto-Negotiation Advertisement Register Virtual PHY to advertise its flow control abilities and auto-negotiate the flow control settings with the SMSC LAN9313/LAN9313i Parallel Detection is used. are dependant on the MII_DUPLEX pin and the duplex_pol_strap_mii Table 13 ...
Page 100
... Virtual PHY in MAC Modes In the MAC modes of operation, an external PHY is connected to the MII interface of the LAN9313/LAN9313i. Because there is an external PHY present, the Virtual PHY is not needed for external configuration. However, the port 0 switch fabric MAC still requires the proper duplex setting. ...
Page 101
... Three Port 10/100 Managed Ethernet Switch with MII Datasheet Chapter 8 Serial Management 8.1 Functional Overview This chapter details the serial management functionality provided by the LAN9313/LAN9313i, which includes the EEPROM I 2 The I C/Microwire EEPROM controller external EEPROM with the system register bus and the EEPROM Loader. Multiple types ...
Page 102
... Note: The EEPROM device powers-up in the erase/write disabled state. To modify the contents of the EEPROM, the EWEN command must first be issued operation is attempted and the EEPROM device does not respond within 30mS, the LAN9313/LAN9313i will time-out, and the EPC_TIMEOUT bit of the (E2P_CMD) will be set. ...
Page 103
... Based on the configuration strap eeprom_size_strap, various sized I varying size ranges are supported by additional bits in the address field (EPC_ADDRESS) of the EEPROM Command Register address bits, while the smaller EEPROMs treat the upper address bits as don’t cares. The EEPROM SMSC LAN9313/LAN9313i Idle Write Register ...
Page 104
... EEPROM SIZE 1 (Note 8. through 2048 4096 x 8 through 65536 x 8 104 DATASHEET Three Port 10/100 Managed Ethernet Switch with MII Datasheet 8.2. EEPROM TYPES 24xx00, 24xx01, 24xx02, 24xx04, 24xx08, 24xx16 24xx32, 24xx64, 24xx128, 24xx256, 24xx512 2 C-Bus Specification for detailed timing SMSC LAN9313/LAN9313i ...
Page 105
... Address Byte Chip / Block R/~W Select Bits Single Byte Addressing SMSC LAN9313/LAN9313i 2 C cycle. data data data can can stable change change Sr Data Valid Re-Start or Ack Condition 2 Figure 8 Cycle is set EEPROM addressing bit order for single and double byte addressing. Control Byte ...
Page 106
... C EEPROM Sequential Byte Reads 106 DATASHEET Three Port 10/100 Managed Ethernet Switch with MII Datasheet 2 is set. The I C master then Data Byte R/~W Double Byte Addressing Read Section 8.2.1, "EEPROM Controller 2 is set. The I C master then Data Byte ... Data Byte ... SMSC LAN9313/LAN9313i ...
Page 107
... For a register level description of a write operation, refer to Operation," on page 102. SMSC LAN9313/LAN9313i is set master will poll the EEPROM to determine when the byte 2 C EEPROM byte write. Poll Cycle Poll Cycle Control Byte Chip / Block R/~W Chip / Block Select Bits ...
Page 108
... Three Port 10/100 Managed Ethernet Switch with MII Datasheet Table EEPROM TYPES 93xx46A 93xx56A, 93xx66A 93xx76A, 93xx86A DATA TO DATA FROM # OF EEPROM EEPROM CLOCKS - (RDY/~BSY (RDY/~BSY Hi Hi (RDY/~BSY (RDY/~BSY) 18 DATA TO DATA FROM # OF EEPROM EEPROM CLOCKS - (RDY/~BSY (RDY/~BSY Hi-Z 12 SMSC LAN9313/LAN9313i 8.3. ...
Page 109
... ERASE (Erase Location) If erase/write operations are enabled in the EEPROM, this command will erase the location selected by the EPC_ADDRESS field of the bit is set if the EEPROM does not respond within 30mS. EECS EECLK EEDO 1 1 EEDI SMSC LAN9313/LAN9313i ADDRESS ADDRESS A10 A10 ...
Page 110
... EWEN command must be issued. EECS EECLK EEDO 1 EEDI Revision 1.7 (06-29-10) EEPROM Command Register (E2P_CMD Figure 8.8 EEPROM ERAL Cycle Figure 8.9 EEPROM EWDS Cycle 110 DATASHEET Three Port 10/100 Managed Ethernet Switch with MII Datasheet is set if the SMSC LAN9313/LAN9313i ...
Page 111
... This command will cause a read of the EEPROM location pointed to by the EPC_ADDRESS field of the EEPROM Command Register Register (E2P_DATA). EECS EECLK EEDO 1 1 EEDI SMSC LAN9313/LAN9313i Figure 8.10 EEPROM EWEN Cycle (E2P_CMD). The result of the read is available in the Figure 8.11 EEPROM READ Cycle ...
Page 112
... A0 D7 Figure 8.12 EEPROM WRITE Cycle to be written to every EEPROM memory location. The EEPROM Command Register (E2P_CMD Figure 8.13 EEPROM WRAL Cycle 112 DATASHEET Three Port 10/100 Managed Ethernet Switch with MII Datasheet D0 is set if the EEPROM does not D0 SMSC LAN9313/LAN9313i ...
Page 113
... Register (E2P_CMD), the EPC_BUSY bit in the While the EEPROM Loader is active, the READY bit of the (HW_CFG) is cleared and no writes to the LAN9313/LAN9313i should be attempted. The operational flow of the EEPROM Loader can be seen in SMSC LAN9313/LAN9313i 2 C/Microwire EEPROM controller, the PHYs, and to the system ...
Page 114
... Byte 12 = A5h Perform register data load loop Figure 8.14 EEPROM Loader Flow Diagram Revision 1.7 (06-29-10) Load PHY registers with N current straps Y Load PHY registers with N current straps 114 DATASHEET Three Port 10/100 Managed Ethernet Switch with MII Datasheet EPC_BUSY = 0 SMSC LAN9313/LAN9313i ...
Page 115
... Auto-negotiation results. SMSC LAN9313/LAN9313i and Table 8.8. If the flag byte is not A5h, these next 4 bytes are skipped Section for more information on the LAN9313/LAN9313i configuration Table 8.8 EEPROM Configuration Bits manual_ manual_mdix auto_mdix_ ...
Page 116
... Register Data Optionally following the configuration strap values, the EEPROM data may be formatted to allow access to the LAN9313/LAN9313i parallel, directly writable registers. Access to indirectly accessible registers (e.g. Switch Engine registers, etc.) is achievable with an appropriate sequence of writes (at the cost of EEPROM space). This data is first preceded with a Burst Sequence Valid Flag (EEPROM byte 12). If this byte has a value of A5h, the data that follows is recognized as a sequence of bursts ...
Page 117
... In order to allow the EEPROM Loader to change the Port 1/2 PHYs and Virtual PHY strap inputs and maintain consistency with the PHY and Virtual PHY registers, the following sequence is used: 1. After power-up or upon a hardware reset (nRST), the straps are sampled into the LAN9313/LAN9313i as specified in page 389. ...
Page 118
... SPI Slave Operation When in MAC/PHY SPI managed mode, the SPI slave interface is used for CPU management of the LAN9313/LAN9313i. All system CSRs are accessible to the CPU in these modes. SPI mode is selected when the mngt_mode_strap[1:0] inputs are set to 11b. The SPI slave interface supports single register and multiple register read and write commands ...
Page 119
... SPI Read Sequence The SPI slave interface of the LAN9313/LAN9313i is selected for reads by first bringing nSCS low. The SI pin should then driven with an 8-bit read instruction, followed by the 8-bit address. On the falling clock edge which follows the rising edge of the last address bit, the SO output is driven starting with the msb of the selected register ...
Page 120
... Section 4.2, "Resets," on page 41 8.4.2 SPI Write Sequence The SPI slave interface of the LAN9313/LAN9313i is selected for writes by first bringing nSCS low. The SI pin should then driven with an 8-bit write instruction, followed by the 8-bit address and then the data. Multiple writes are performed by continuing the clock pulses and input data while nSCS is low. ...
Page 121
... The control byte consists of a 7-bit slave address and a 1-bit read/write indication (R/~W). The slave address used by the LAN9313/LAN9313i is 0001010b, written as SA6 (first bit on the wire) through SA0 (last bit on the wire). Assuming the slave address in the control byte matches this address, the control byte is acknowledged by the LAN9313/LAN9313i ...
Page 122
... If the read/write indication in the control byte (indicating a read), the LAN9313/LAN9313i will start sending data following the control byte acknowledgement. Note: All registers are accessed as DWORDs. Appending two 0 bits to the address field will form the register address ...
Page 123
... C Slave Write Sequence Following the device addressing, as detailed in LAN9313/LAN9313i when the master continues to send data bytes. Each byte is acknowledged by the LAN9313/LAN9313i. Following the fourth byte of the sequence, the master may either send another start condition or halt the sequence with a stop condition. The internal register address is unchanged following a single write ...
Page 124
... Revision 1.7 (06-29-10) Address Byte Data Byte Single Register Write ...Data m Byte Data 1 Byte .. . .. . Multiple Register Writes 2 Figure 8 Slave Writes 124 DATASHEET Three Port 10/100 Managed Ethernet Switch with MII Datasheet Data Byte... ...Data Byte .. . Data m+1 Byte... ...Data n Byte .. . SMSC LAN9313/LAN9313i ...
Page 125
... The SMI frame format can be seen in LAN9313/LAN9313i uses the PHY Address field bits 3:0 as the system register address bits 9:6, and the Register Address field as the system register address bits 5:1. Therefore, Register Address field bit 0 is used as the upper/lower word select ...
Page 126
... If a read to the same word is performed, the combined data read pair is invalid and should be re-read. This is not a fatal error. The LAN9313/LAN9313i will simply reset the read counters, and restart a new cycle on the next read. Note: Select registers are readable as 16-bit registers, as noted in their register descriptions. For these registers, only one 16-bit read may be performed without the need to read the other word ...
Page 127
... PHY drives the second bit of the turn-around time to 0, and then drives the msb of the read data in the following cycle. For a write, the LAN9313/LAN9313i drives the first bit of the turnaround time to 1, the second bit of the turnaround time to 0, and then the msb of the write data in the following clock cycle ...
Page 128
... MII pins, or PMI) is connected to the slaves (PHY via MII pins, Port 1/2 PHYs, Virtual PHY, and SMI slave) dependant on the selected management mode of the LAN9313/LAN9313i. The MII mode multiplexer also performs the multiplexing of the read data signals from the slaves and controls the output enable of the MII pins ...
Page 129
... MDCLK PHY1 MDI MDO MDIO_ DIR MDCLK Management Mode Selection Figure 9.2 MII Mux Management Path Connections - MAC Mode SMI Managed SMSC LAN9313/LAN9313i and Section 8.2.4, "EEPROM Loader," on page 113 Management Mode Selection MDO MDCLK MDI MDO_EnN PMI Parallel Slave ...
Page 130
... MDO MDCLK 130 DATASHEET Three Port 10/100 Managed Ethernet Switch with MII Datasheet 2 C/SPI slave interfaces or the EEPROM and Section 8.2.4, "EEPROM MII Pins MDIO_DIR MDO MDIO MDI MDC_DIR MDC_ OUT MDC MDC_IN MDI MDO_EnN PMI Parallel Slave 2 C/SPI Managed SMSC LAN9313/LAN9313i ...
Page 131
... MDIO_ DIR MDCLK PHY1 MDI MDO MDIO_ DIR MDCLK Management Mode Selection Figure 9.4 MII Mux Management Path Connections - PHY Mode Unmanaged SMSC LAN9313/LAN9313i for additional information. Management Mode Selection MDO MDCLK 131 DATASHEET Section 8.2.4, "EEPROM MII Pins MDIO_DIR MDO ...
Page 132
... Three Port 10/100 Managed Ethernet Switch with MII and Section 8.2.4, "EEPROM Loader," on page 113 Management Mode Selection MDO MDCLK MDI MDO_EnN PMI Parallel Slave 132 DATASHEET Datasheet Section for MII Pins MDIO_DIR MDO MDIO MDI MDC_DIR MDC_ OUT MDC MDC_IN SMSC LAN9313/LAN9313i ...
Page 133
... MDCLK PHY1 MDI MDO MDIO_ DIR MDCLK Management Mode Selection Figure 9.6 MII Mux Management Path Connections - PHY Mode I SMSC LAN9313/LAN9313i Section 8.3, "SPI/I2C Slave Controller," on page 118 for additional information. Management Mode Selection MDO MDCLK MDI PMI Parallel Slave ...
Page 134
... Time stamping is supported on all ports, with an individual IEEE 1588 Time Stamp module connected to each port via the MII bus. Any port may function as a master or a slave clock per the IEEE 1588 specification, and the LAN9313/LAN9313i as a whole may function as a boundary clock. ...
Page 135
... Three Port 10/100 Managed Ethernet Switch with MII Datasheet 10.1.2 Block Diagram The LAN9313/LAN9313i IEEE 1588 implementation is illustrated in following major function blocks: IEEE 1588 Time Stamp These three identical blocks provide time stamping functions on all switch fabric ports. IEEE 1588 Clock This block provides a 64-bit tunable clock that is used as the time source for all IEEE 1588 time stamp related functions ...
Page 136
... PHY. This is consistent with the point-of-view of where the partner clock resides (LAN9313/LAN9313i receives packets from the partner via the PHY, etc.). For the time stamp module connected to the external MII port (Port 0), the definition of transmit and receive is reversed. Receive is defined as data from the switch fabric, while transmit is defined as data to the switch fabric ...
Page 137
... Interrupt Status and Enable Register (1588_INT_STS_EN) 13.1.4.22, "1588 Configuration Register (1588_CONFIG)," on page 185 the capture locking related bits. SMSC LAN9313/LAN9313i Table 10.2 details the time stamp capture delay as a function of the Chapter 7, "Ethernet PHYs," on page 84 Table 10.2 Time Stamp Capture Delay Table 10 ...
Page 138
... PTP Message Detection In order to provide the most flexibility, loose packet type matching is used by the LAN9313/LAN9313i. This assumes that for all packets received with a valid FCS, only the MAC destination address is required to qualify them as a PTP message. For Ethernet, four multicast addresses are specified in the PTP protocol: 224 ...
Page 139
... IEEE 1588 Clock The 64-bit IEEE 1588 clock is the time source for all IEEE 1588 related functions of the LAN9313/LAN9313i readable and writable by the host via the (1588_CLOCK_HI) and In order to accurately read this clock, a special procedure must be followed. Since two DWORD reads are required to fully read the 64-bit clock, the possibility exists that as the lower 32-bits roll over, a wrong intermediate value could be read ...
Page 140
... IEEE 1588 interrupts and enables. Interrupt Status Register 1588 Interrupt Status and Enable Register (1588_INT_STS_EN) Section 12.2.2, "GPIO Interrupts," on for additional information on the 140 DATASHEET Datasheet checked to determine (1588 Clock Target and 1588 Clock Target Section 12.2.1, "GPIO (INT_STS). SMSC LAN9313/LAN9313i ...
Page 141
... This chapter details the LAN9313/LAN9313i General Purpose Timer (GPT) and the Free-Running Clock. 11.1 General Purpose Timer The LAN9313/LAN9313i provides a 16-bit programmable General Purpose Timer that can be used to generate periodic system interrupts. The resolution of this timer is 100uS. The GPT loads the GPT_LOAD field of the ...
Page 142
... DATASHEET Three Port 10/100 Managed Ethernet Switch with MII Datasheet General Purpose I/O Interrupt for additional information. General Purpose I/O Configuration (GPIO_DATA_DIR). The (GPIO_DATA_DIR). When General Purpose I/O Data & (GPIO_DATA_DIR). For GPIOs General and the 1588_GPIO_OE[9:8] bits in SMSC LAN9313/LAN9313i ...
Page 143
... General Purpose I/O Configuration Register 12.2.2 GPIO Interrupts Each GPIO of the LAN9313/LAN9313i provides the ability to trigger a unique GPIO interrupt in the General Purpose I/O Interrupt Status and Enable Register GPIO_INT[11:0] bits of this register provides the current status of the corresponding interrupt, and each interrupt is enabled by setting the corresponding GPIO_INT_EN[11:0] bit ...
Page 144
... LED Configuration Register Table 12.1 followed by a detailed LED Configuration Register and its related straps, refer to 159. 10b 11b Activity - Port 2 Link - Port 2 TXEN Port 2 Port 2 Speed RXDV Port 2 Port 2 Activity TXEN Port 1 Port 0 Link RXDV Port 1 Port 0 SMSC LAN9313/LAN9313i LED ...
Page 145
... RXDV Port 0 - Non-stretched RXDV signal from the external MII pins to the switch fabric. TXEN - Non-stretched TXEN signal from the switch fabric to the PHY. RXDV - Non-stretched RXDV signal from the PHY to the switch fabric. SMSC LAN9313/LAN9313i LED_CFG[9:8] (LED_FUN[1:0]) Full-duplex / Collision Full-duplex / Collision ...
Page 146
... Note: Register bit type definitions are provided in Note: Not all LAN9313/LAN9313i registers are memory mapped or directly addressable. For details on the accessibility of the various LAN9313/LAN9313i registers, refer the register sub-sections listed above. ...
Page 147
... The System CSR’s are directly addressable memory mapped registers with a base address offset range of 050h to 2DCh. These registers are accessed through the I MIIM/SMI serial interface. For more information on the various LAN9313/LAN9313i modes and their corresponding address configurations, see Table 13.1 lists the System CSR’ ...
Page 148
... Port 0 1588 Source UUID Low-DWORD Receive Capture Register, Section 13.1.4.4 Port 0 1588 Clock High-DWORD Transmit Capture Register, Section 13.1.4.5 Port 0 1588 Clock Low-DWORD Transmit Capture Register, Section 13.1.4.6 148 DATASHEET Datasheet Section 13.1.4.3 Section 13.1.4.7 Section 13.1.4.3 Section 13.1.4.7 Section 13.1.4.3 SMSC LAN9313/LAN9313i ...
Page 149
... E2P_CMD 1B8h E2P_DATA 1BCh LED_CFG 1C0h VPHY_BASIC_CTRL 1C4h VPHY_BASIC_STATUS SMSC LAN9313/LAN9313i REGISTER NAME Port 0 1588 Sequence ID, Source UUID High-WORD Transmit Capture Register, Port 0 1588 Source UUID Low-DWORD Transmit Capture Register, Section 13.1.4.8 GPIO 8 1588 Clock High-DWORD Capture Register, Section 13.1.4.9 GPIO 8 1588 Clock Low-DWORD Capture Register, Section 13 ...
Page 150
... Switch MAC Address High Register, Switch MAC Address Low Register, Reset Control Register, Section 13.1.8.7 Reserved for Future Use Switch Engine CSR Interface Direct Data Register, Section 13.1.5.8 Reserved for Future Use 150 DATASHEET Datasheet Section 13.1.7.3 Section 13.1.7.4 Section 13.1.5.6 Section 13.1.5.7 SMSC LAN9313/LAN9313i ...
Page 151
... Datasheet 13.1.1 Interrupts This section details the interrupt related System CSR’s. These registers control, configure, and monitor the IRQ interrupt output pin and the various LAN9313/LAN9313i interrupt sources. For more information on the LAN9313/LAN9313i interrupts, refer to 13.1.1.1 Interrupt Configuration Register (IRQ_CFG) Offset: This read/write register configures and indicates the state of the IRQ signal ...
Page 152
... Note 13.1 Register bits designated as NASR are not reset when the DIGITAL_RST bit in the Control Register (RESET_CTL) Revision 1.7 (06-29-10) Three Port 10/100 Managed Ethernet Switch with MII DESCRIPTION is set. 152 DATASHEET Datasheet TYPE DEFAULT R/W 0b NASR Note 13 R/W 0b NASR Note 13.1 Reset SMSC LAN9313/LAN9313i ...
Page 153
... Register (INT_EN) is set high. Writing a one clears this interrupt. 30 Device Ready (READY) This interrupt indicates that the LAN9313/LAN9313i is ready to be accessed after a power-up or reset condition. 29 1588 Interrupt Event (1588_EVNT) This bit indicates an interrupt event from the IEEE 1588 module. This bit ...
Page 154
... Revision 1.7 (06-29-10) Three Port 10/100 Managed Ethernet Switch with MII 05Ch Size: Interrupt Status Register (INT_STS) bits, which mimic the layout of this register. DESCRIPTION 154 DATASHEET Datasheet 32 bits register TYPE DEFAULT R/W 0b R/W 0b R/W 0b R/W 0b R SMSC LAN9313/LAN9313i ...
Page 155
... GPIO 8 Clock Event Polarity (GPIO_EVENT_POL_8) This bit determines if the 1588 clock event output on GPIO 8 is active high or low. 0: 1588 clock event output active low 1: 1588 clock event output active high SMSC LAN9313/LAN9313i 1E0h Size: DESCRIPTION 1588 Interrupt Status and Enable Register General (GPIO_INT_STS_EN) ...
Page 156
... GPIOx Clock Event Polarity Revision 1.7 (06-29-10) Three Port 10/100 Managed Ethernet Switch with MII DESCRIPTION 1588 Clock Event Pin State no not driven yes driven low no driven low yes not driven 156 DATASHEET Datasheet TYPE DEFAULT R/W 0h SMSC LAN9313/LAN9313i ...
Page 157
... For GPIOs 11-10 and 7-0, the pin direction is determined by the GPDIR bits of this register. For GPIOs 9 and 8, the pin direction is determined by the GPDIR bits and the 1588_GPIO_OE bits in the Configuration Register (GPIO_CFG). SMSC LAN9313/LAN9313i 1E4h Size: DESCRIPTION General Purpose I/O 157 ...
Page 158
... Three Port 10/100 Managed Ethernet Switch with MII 1E8h Size: Interrupt Status Register Interrupt Enable Register (INT_EN) Chapter 5, "System Interrupts," on page 52 DESCRIPTION in order to cause the General Purpose I/O Configuration 158 DATASHEET Datasheet 32 bits (INT_STS). Writing a 1 must also be set in order TYPE DEFAULT R/WC 0h SMSC LAN9313/LAN9313i for ...
Page 159
... Note 13.3 The default value of this field is determined by the configuration strap LED_en_strap[7:0]. Configuration strap values are latched on power-on reset or nRST de-assertion. Some configuration straps can be overridden by values from the EEPROM Loader. Refer to Section 4.2.4, "Configuration Straps," on page 45 SMSC LAN9313/LAN9313i 1BCh Size: DESCRIPTION 144 ...
Page 160
... EEPROM This section details the EEPROM related System CSR’s. These registers should only be used if an EEPROM has been connected to the LAN9313/LAN9313i. Refer to chapter Master EEPROM Controller," on page 101 Microwire) of the EEPROM Controller (EPC). 13.1.3.1 EEPROM Command Register (E2P_CMD) Offset: This read/write register is used to control the read and write operations of the serial EEPROM ...
Page 161
... RELOAD operation will fail. The CFG_LOADED bit indicates a successful load. Following this command, the device will enter the not ready state. The READY bit in the Hardware Configuration Register (HW_CFG) to determine then the RELOAD is complete. 27:19 RESERVED SMSC LAN9313/LAN9313i DESCRIPTION [28] Operation 0 READ 1 ...
Page 162
... This field is used by the EEPROM Controller to address a specific memory location in the serial EEPROM. This address must be byte aligned. Revision 1.7 (06-29-10) Three Port 10/100 Managed Ethernet Switch with MII DESCRIPTION 162 DATASHEET Datasheet TYPE DEFAULT RO 0b R/WC 0b R/WC 0b R/W 0000h SMSC LAN9313/LAN9313i ...
Page 163
... This read/write register is used in conjunction with the perform read and write operations with the serial EEPROM. BITS 31:8 RESERVED 7:0 EEPROM Data (EEPROM_DATA) This field contains the data read from or written to the EEPROM. SMSC LAN9313/LAN9313i 1B8h Size: EEPROM Command Register (E2P_CMD) DESCRIPTION 163 DATASHEET 32 bits ...
Page 164
... Sync or Delay_Req packet. Note: The selection between Sync or Delay_Req packets is based on the corresponding master/slave bit in the Note: There are multiple instantiations of this register, one for each port of the LAN9313/LAN9313i. Refer to Section 13.1.4 Note: For Port 0(External MII), receive is defined as data from the switch fabric, while transmit is to the switch fabric ...
Page 165
... Sync or Delay_Req packet. Note: The selection between Sync or Delay_Req packets is based on the corresponding master/slave bit in the Note: There are multiple instantiations of this register, one for each port of the LAN9313/LAN9313i. Refer to Section 13.1.4 Note: For Port 0(External MII), receive is defined as data from the switch fabric, while transmit is to the switch fabric ...
Page 166
... Delay_Req packet. Note: The selection between Sync or Delay_Req packets is based on the corresponding master/slave bit in the Note: There are multiple instantiations of this register, one for each port of the LAN9313/LAN9313i. Refer to Section 13.1.4 Note: For Port 0(External MII), receive is defined as data from the switch fabric, while transmit is to the switch fabric ...
Page 167
... Delay_Req packet. Note: The selection between Sync or Delay_Req packets is based on the corresponding master/slave bit in the Note: There are multiple instantiations of this register, one for each port of the LAN9313/LAN9313i. Refer to Section 13.1.4 Note: For Port 0(External MII), receive is defined as data from the switch fabric, while transmit is to the switch fabric ...
Page 168
... Sync or Delay_Req packet. Note: The selection between Sync or Delay_Req packets is based on the corresponding master/slave bit in the Note: There are multiple instantiations of this register, one for each port of the LAN9313/LAN9313i. Refer to Section 13.1.4 Note: For Port 0(External MII), receive is defined as data from the switch fabric, while transmit is to the switch fabric ...
Page 169
... Sync or Delay_Req packet. Note: The selection between Sync or Delay_Req packets is based on the corresponding master/slave bit in the Note: There are multiple instantiations of this register, one for each port of the LAN9313/LAN9313i. Refer to Section 13.1.4 Note: For Port 0(External MII), receive is defined as data from the switch fabric, while transmit is to the switch fabric ...
Page 170
... Delay_Req packet. Note: The selection between Sync or Delay_Req packets is based on the corresponding master/slave bit in the Note: There are multiple instantiations of this register, one for each port of the LAN9313/LAN9313i. Refer to Section 13.1.4 Note: For Port 0(External MII), receive is defined as data from the switch fabric, while transmit is to the switch fabric ...
Page 171
... Delay_Req packet. Note: The selection between Sync or Delay_Req packets is based on the corresponding master/slave bit in the Note: There are multiple instantiations of this register, one for each port of the LAN9313/LAN9313i. Refer to Section 13.1.4 Note: For Port 0(External MII), receive is defined as data from the switch fabric, while transmit is to the switch fabric ...
Page 172
... This field contains the high 32-bits of the timestamp upon activation of GPIO 8. Revision 1.7 (06-29-10) Three Port 10/100 Managed Ethernet Switch with MII 160h Size: GPIO 8 1588 Clock Low-DWORD Capture Register form the 64-bit GPIO 8 timestamp capture. DESCRIPTION 172 DATASHEET Datasheet 32 bits TYPE DEFAULT RO 00000000h SMSC LAN9313/LAN9313i ...
Page 173
... This read only register combined with the (1588_CLOCK_HI_CAPTURE_GPIO_8) BITS 31:0 Timestamp Low (TS_LO) This field contains the low 32-bits of the timestamp upon activation of GPIO 8. SMSC LAN9313/LAN9313i 164h Size: GPIO 8 1588 Clock High-DWORD Capture Register form the 64-bit GPIO 8 timestamp capture. DESCRIPTION 173 ...
Page 174
... This field contains the high 32-bits of the timestamp upon activation of GPIO 9. Revision 1.7 (06-29-10) Three Port 10/100 Managed Ethernet Switch with MII 168h Size: GPIO 9 1588 Clock Low-DWORD Capture Register form the 64-bit GPIO 9 timestamp capture. DESCRIPTION 174 DATASHEET Datasheet 32 bits TYPE DEFAULT RO 00000000h SMSC LAN9313/LAN9313i ...
Page 175
... This read only register combined with the (1588_CLOCK_HI_CAPTURE_GPIO_9) BITS 31:0 Timestamp Low (TS_LO) This field contains the low 32-bits of the timestamp upon activation of GPIO 9. SMSC LAN9313/LAN9313i 16Ch Size: GPIO 9 1588 Clock High-DWORD Capture Register form the 64-bit GPIO 9 timestamp capture. DESCRIPTION 175 ...
Page 176
... Size: 1588 Clock Low-DWORD Register (1588_CLOCK_LO) accordingly. Refer to Chapter 10, "IEEE 1588 Hardware Time Stamp Unit," DESCRIPTION 1588 Clock Low-DWORD Register (1588_CLOCK_LO) is set. 176 DATASHEET Datasheet 32 bits form the 1588 Clock Addend Register TYPE DEFAULT R/W 00000000h must be SMSC LAN9313/LAN9313i ...
Page 177
... Note: Both this register and the written for either to be affected. Note: The value read is the saved value of the 1588 Clock when the 1588_CLOCK_SNAPSHOT bit in the 1588 Command Register (1588_CMD) SMSC LAN9313/LAN9313i 174h Size: 1588 Clock High-DWORD Register (1588_CLOCK_HI) accordingly. Refer to Chapter 10, " ...
Page 178
... This allows the base 100MHz frequency of the 64-bit 1588 Clock to be adjusted accordingly. Revision 1.7 (06-29-10) Three Port 10/100 Managed Ethernet Switch with MII 178h Size: DESCRIPTION 178 DATASHEET Datasheet 32 bits for details on how to properly use TYPE DEFAULT R/W 00000000h SMSC LAN9313/LAN9313i ...
Page 179
... BITS 31:0 Clock Target High (CLOCK_TARGET_HI) This field contains the high 32-bits of the 64-bit 1588 Clock Compare value. Note: Both this (1588_CLOCK_TARGET_LO) SMSC LAN9313/LAN9313i 17Ch Size form the 64-bit 1588 Clock Target value. The 1588 Clock Target value DESCRIPTION register and ...
Page 180
... Clock Target value. The 1588 Clock Target value is DESCRIPTION register and the 1588 Clock must be written for either to be affected. 180 DATASHEET Three Port 10/100 Managed Ethernet Switch with MII Datasheet 32 bits for additional information. TYPE DEFAULT R/W 00000000h Target High-DWORD Register SMSC LAN9313/LAN9313i ...
Page 181
... This field contains the high 32-bits of the 64-bit 1588 Clock Target Reload value that is reloaded to the 1588 Clock Compare value. Note: Both this register and the (1588_CLOCK_TARGET_RELOAD_LO) SMSC LAN9313/LAN9313i 184h Size: 1588 Clock Target Reload/Add Low-DWORD Register form the 64-bit 1588 Clock Target Reload value. The 1588 Reload/Add (RELOAD_ADD) Chapter 10, " ...
Page 182
... Clock Target Reload value. The 1588 1588 Configuration Register (1588_CONFIG). Refer to for additional information. DESCRIPTION and the 1588 Clock Target must be written for either to be affected. 182 DATASHEET Datasheet 32 bits Reload/Add Chapter 10, "IEEE TYPE DEFAULT R/W 00000000h Reload High-DWORD Register SMSC LAN9313/LAN9313i ...
Page 183
... Auxiliary MAC Address High-WORD Register (1588_AUX_MAC_HI) Offset: This read/write register combined with the (1588_AUX_MAC_LO) address can be enabled for each port of the LAN9313/LAN9313i via their respective User Defined MAC Address Enable bit in the "IEEE 1588 Hardware Time Stamp Unit," on page 134 BITS ...
Page 184
... Auxiliary MAC Address Low-DWORD Register (1588_AUX_MAC_LO) Offset: This read/write register combined with the (1588_AUX_MAC_HI) address can be enabled for each port of the LAN9313/LAN9313i via their respective User Defined MAC Address Enable bit in the "IEEE 1588 Hardware Time Stamp Unit," on page 134 BITS ...
Page 185
... When set, Port time clock master and captures timestamps when a Sync packet is transmitted and when a Delay_Req is received. When cleared, Port time clock slave and captures timestamps when a Delay_Req packet is transmitted and when a Sync packet is received. SMSC LAN9313/LAN9313i 194h Size: DESCRIPTION 185 ...
Page 186
... Disables primary MAC address on Port 0 1: Enables MAC address 01:00:5E:00:01: PTP address on Port 0 Revision 1.7 (06-29-10) Three Port 10/100 Managed Ethernet Switch with MII DESCRIPTION 186 DATASHEET Datasheet TYPE DEFAULT R/W 1b R/W 0b R/W 0b R/W 0b R/W 0b R/W 1b R/W 1b R/W 0b R/W 1b SMSC LAN9313/LAN9313i ...
Page 187
... This bit enables/disables the GPIO 9 lock. This lock prevents a 1588 capture from overwriting the Clock value if the 1588_GPIO9 interrupt in the Interrupt Status and Enable Register (1588_INT_STS_EN) due to a previous capture. 0: Disables GPIO 9 Lock 1: Enables GPIO 9 Lock SMSC LAN9313/LAN9313i DESCRIPTION is already set 187 DATASHEET TYPE ...
Page 188
... General Purpose I/O Configuration and 1588 Clock Target Low-DWORD Register are loaded from the 1588 Clock Target when a clock target compare event 188 DATASHEET Datasheet TYPE DEFAULT R/W 1b 1588 R/W 00b R/W 00b R/W 0b and SMSC LAN9313/LAN9313i ...
Page 189
... MII the matches the configured PTP packet and the 1588 clock was captured. Note: For Port 0, receive is defined as data from the switch fabric, while transmit is to the switch fabric. SMSC LAN9313/LAN9313i 198h Size: Interrupt Status Register Interrupt Enable Register (INT_EN) DESCRIPTION ...
Page 190
... Section 12.2, "GPIO Operation," on page 142 additional information. Revision 1.7 (06-29-10) Three Port 10/100 Managed Ethernet Switch with MII DESCRIPTION General Purpose register. General Purpose register. and 1588 Clock Target Low-DWORD Register for 190 DATASHEET Datasheet TYPE DEFAULT R/WC 0b R/WC 0b R/WC 0b R/WC 0b SMSC LAN9313/LAN9313i ...
Page 191
... Clock Snapshot (1588_CLOCK_SNAPSHOT) Setting this bit causes the current (1588_CLOCK_HI) and 1588 Clock Low-DWORD Register (1588_CLOCK_LO) values to be saved so they can be read. SMSC LAN9313/LAN9313i 19Ch Size: 1588 Clock High-DWORD Register 1588 Clock Low-DWORD Register for additional information. DESCRIPTION 1588 Clock High-DWORD Register ...
Page 192
... Section 6.2.3, "Flow Control Enable Logic," on page 60 DESCRIPTION 192 DATASHEET Datasheet Table 13.12. For 57. For detailed descriptions of Section 13.3, 32 bits for additional Section 13.2.2.5, on page 239) TYPE DEFAULT RO - R/W Note 13.4 RO Note 13.5 RO Note 13.5 RO Note 13.5 R/W Note 13.6 SMSC LAN9313/LAN9313i ...
Page 193
... Note 13.7 The default value of this field is determined by the manual_FC_strap_1 configuration strap. The strap values are loaded during reset and can be re-written by the EEPROM Loader. Once the EEPROM Loader re-writes the values, this register is updated with the new values. See SMSC LAN9313/LAN9313i DESCRIPTION for additional information. Section 4.2.4, "Configuration Straps," on page 45 ...
Page 194
... Section 6.2.3, "Flow Control Enable Logic," on page 60 DESCRIPTION 194 DATASHEET Datasheet 32 bits for additional Section 13.2.2.5, on page 239) TYPE DEFAULT RO - R/W Note 13.8 RO Note 13.9 RO Note 13.9 RO Note 13.9 R/W Note 13.10 R/W Note 13.10 R/W Note 13.11 SMSC LAN9313/LAN9313i ...
Page 195
... Note 13.11 The default value of this field is determined by the manual_FC_strap_2 configuration strap. The strap values are loaded during reset and can be re-written by the EEPROM Loader. Once the EEPROM Loader re-writes the values, this register is updated with the new values. See SMSC LAN9313/LAN9313i for additional information. Section 4.2.4, "Configuration Straps," on page 45 195 DATASHEET for more information ...
Page 196
... Section 6.2.3, "Flow Control Enable Logic," on page 60 Section 13.1.7.5, "Virtual PHY Auto-Negotiation Advertisement are not affected by the values of this register. DESCRIPTION 196 DATASHEET Datasheet 32 bits TYPE DEFAULT RO - R/W Note 13.12 RO Note 13.13 RO Note 13.13 RO Note 13.13 R/W Note 13.14 R/W Note 13.14 SMSC LAN9313/LAN9313i for ...
Page 197
... Loader. Once the EEPROM Loader re-writes the value, this register is updated with the new values. In MAC mode, this bit is not re-written by the EEPROM Loader and has a default value of “1”. See information. SMSC LAN9313/LAN9313i DESCRIPTION for more information. for additional information. ...
Page 198
... Switch Fabric CSR’s. Refer to DESCRIPTION CSR Address (CSR_ADDR[15:0]) (SWITCH_CSR_CMD). If R/nW is 198 DATASHEET Three Port 10/100 Managed Ethernet Switch with MII Datasheet 32 bits for details on the registers TYPE DEFAULT R/W 00000000h Switch SMSC LAN9313/LAN9313i ...
Page 199
... SWITCH_CSR_DATA register. 0: Disable Auto Decrement 1: Enable Auto Decrement 27:20 RESERVED SMSC LAN9313/LAN9313i 1B0h Size: Switch Fabric CSR Interface Data Register to control the read and write operations to the various Switch Fabric CSR’s. DESCRIPTION (SWITCH_CSR_DATA) ...
Page 200
... Refer to Accessible Switch Control and Status Registers,” on page 253 Switch Fabric CSR addresses. Revision 1.7 (06-29-10) Three Port 10/100 Managed Ethernet Switch with MII DESCRIPTION Table 13.12, “Indirectly for a list of 200 DATASHEET Datasheet TYPE DEFAULT R/W 0h R/W 00h SMSC LAN9313/LAN9313i ...