LAN9313I-NZW SMSC, LAN9313I-NZW Datasheet - Page 43

• Manufacturer Part Number: LAN9313I-NZW
• Description: Ethernet ICs Three Port 10/100 Ethernet Switch
• Manufacturer: SMSC
• Type: Three Port Managed Ethernet Switchr

Specifications of LAN9313I-NZW

• Ethernet Connection Type: 10 Base-T, 100 Base-TX
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Product: Ethernet Switches
• Number Of Transceivers: 1
• Standard Supported: 802.3, 802.3u
• Data Rate: 10 Mbps, 100 Mbps
• Supply Voltage (max): 3.3 V
• Supply Voltage (min): 0 V
• Supply Current (max): 155 mA, 270 mA
• Maximum Operating Temperature: + 70 C
• Package / Case: TQFP-100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Three Port 10/100 Managed Ethernet Switch with MII
Datasheet
SMSC LAN9313/LAN9313i
4.2.1.2
4.2.2
4.2.2.1
4.2.3
nRST Pin Reset
Driving the nRST input pin low initiates a chip-level reset. This event resets all circuitry within the
device. Use of this reset input is optional, but when used, it must be driven for the period of time
specified in
are latched, and the EEPROM Loader is run as a result of this reset.
A nRST pin reset typically takes approximately 760uS, plus additional time (91uS for I
Microwire) per byte of data loaded from the EEPROM via the EEPROM Loader. A full EEPROM load
(64KB for I
58mS for Microwire EEPROM.
Note: The nRST pin is pulled-high internally. If unused, this signal can be left unconnected. Do not
Please refer to
Multi-Module Resets
Multi-module resets activate multiple internal resets, but do not reset the entire chip. Configuration
straps are not latched upon multi-module resets. A multi-module reset is initiated by assertion of the
following:
Multi-module reset/configuration completion can be determined by first polling the
Register
Once the returned data is the correct byte ordering value, the serial interface resets have completed.
The completion of the entire chip-level reset must then be determined by polling the READY bit of the
Hardware Configuration Register (HW_CFG)
reset has completed and the device is ready to be accessed.
With the exception of the
(BYTE_TEST), and
forbidden while the READY bit is cleared. Writes to any address are invalid until the READY bit is set.
Note: The digital reset does not reset register bits designated as NASR.
Digital Reset (DIGITAL_RST)
A digital reset is performed by setting the DIGITAL_RST bit of the
(RESET_CTL). A digital reset will reset all LAN9313/LAN9313i sub-modules except the Ethernet PHYs
(Port 1 PHY, Port 2 PHY, and Virtual PHY). The EEPROM Loader will automatically run following this
reset. Configuration straps are not latched as a result of a digital reset.
A digital reset typically takes approximately 760uS, plus additional time (91uS for I
Microwire) per byte of data loaded from the EEPROM via the EEPROM Loader. A full EEPROM load
(64KB for I
58mS for Microwire EEPROM.
Single-Module Resets
A single-module reset will reset only the specified module. Single-module resets do not latch the
configuration straps or initiate the EEPROM Loader. A single-module reset is initiated by assertion of
the following:
Digital Reset (DIGITAL_RST)
Port 2 PHY Reset
Port 1 PHY Reset
Virtual PHY Reset
rely on internal pull-up resistors to drive signals external to the device.
(BYTE_TEST). The returned data will be invalid until the serial interface resets are complete.
2
2
Section 14.5.2, "Reset and Configuration Strap Timing," on page
C, 2KB for Microwire) will complete in approximately 6.0 seconds for I
C, 2KB for Microwire) will complete in approximately 6.0 seconds for I
Section Table 3.8, "Miscellaneous Pins," on page 39
Reset Control Register
Hardware Configuration Register
DATASHEET
43
(RESET_CTL), read access to any internal resources is
until it is set. When set, the READY bit indicates that the
(HW_CFG),
for a description of the nRST pin.
Byte Order Test Register
Reset Control Register
389. Configuration straps
Revision 1.7 (06-29-10)
2
2
C EEPROM, and
C EEPROM, and
Byte Order Test
2
2
C, 28uS for
C, 28uS for