LAN9313I-NZW SMSC, LAN9313I-NZW Datasheet - Page 141

• Manufacturer Part Number: LAN9313I-NZW
• Description: Ethernet ICs Three Port 10/100 Ethernet Switch
• Manufacturer: SMSC
• Type: Three Port Managed Ethernet Switchr

Specifications of LAN9313I-NZW

• Ethernet Connection Type: 10 Base-T, 100 Base-TX
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Product: Ethernet Switches
• Number Of Transceivers: 1
• Standard Supported: 802.3, 802.3u
• Data Rate: 10 Mbps, 100 Mbps
• Supply Voltage (max): 3.3 V
• Supply Voltage (min): 0 V
• Supply Current (max): 155 mA, 270 mA
• Maximum Operating Temperature: + 70 C
• Package / Case: TQFP-100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Three Port 10/100 Managed Ethernet Switch with MII
Datasheet
Chapter 11 General Purpose Timer & Free-Running Clock
SMSC LAN9313/LAN9313i
11.1
11.2
This chapter details the LAN9313/LAN9313i General Purpose Timer (GPT) and the Free-Running
Clock.
The LAN9313/LAN9313i provides a 16-bit programmable General Purpose Timer that can be used to
generate periodic system interrupts. The resolution of this timer is 100uS.
The GPT loads the
GPT_LOAD field of the
TIMER_EN bit of the
a chip-level reset, or when the TIMER_EN bit changes from asserted (1) to de-asserted (0), the
GPT_LOAD field is initialized to FFFFh. The
also initialized to FFFFh on reset. Software can write a pre-load value into the GPT_LOAD field at any
time (e.g. before or after the TIMER_EN bit is asserted).
Once enabled, the GPT counts down until it reaches 0000h, or until a new pre-load value is written to
the GPT_LOAD field. At 0000h, the counter wraps around to FFFFh, asserts the GPT interrupt status
bit (GPT_INT) in the
is set in the
Once this bit is asserted, it can only be cleared by writing a 1 to the bit. Refer to
Purpose Timer Interrupt," on page 55
The Free-Running Clock (FRC) is a simple 32-bit up-counter that operates from a fixed 25MHz clock.
The current FRC value can be read via the
assertion of a chip-level reset, this counter is cleared to zero. On de-assertion of a reset, the counter
is incremented once for every 25MHz clock cycle. When the maximum count has been reached, the
counter rolls over to zeros. The FRC does not generate interrupts.
Note: The free running counter can take up to 160nS to clear after a reset event.
General Purpose Timer
Free-Running Clock
Interrupt Status Register
Interrupt Status Register
General Purpose Timer Count Register (GPT_CNT)
General Purpose Timer Configuration Register (GPT_CFG)
General Purpose Timer Configuration Register (GPT_CFG)
DATASHEET
for additional information on the GPT interrupt.
(INT_STS)), and continues counting. GPT_INT is a sticky bit.
141
Free Running 25MHz Counter Register
General Purpose Timer Count Register (GPT_CNT)
(INT_STS), asserts the IRQ interrupt (if GPT_INT_EN
Section 5.2.5, "General
with the value in the
Revision 1.7 (06-29-10)
is asserted (1). On
(FREE_RUN). On
when the
is