LAN9313I-NZW SMSC, LAN9313I-NZW Datasheet - Page 137

• Manufacturer Part Number: LAN9313I-NZW
• Description: Ethernet ICs Three Port 10/100 Ethernet Switch
• Manufacturer: SMSC
• Type: Three Port Managed Ethernet Switchr

Specifications of LAN9313I-NZW

• Ethernet Connection Type: 10 Base-T, 100 Base-TX
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Product: Ethernet Switches
• Number Of Transceivers: 1
• Standard Supported: 802.3, 802.3u
• Data Rate: 10 Mbps, 100 Mbps
• Supply Voltage (max): 3.3 V
• Supply Voltage (min): 0 V
• Supply Current (max): 155 mA, 270 mA
• Maximum Operating Temperature: + 70 C
• Package / Case: TQFP-100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Three Port 10/100 Managed Ethernet Switch with MII
Datasheet
SMSC LAN9313/LAN9313i
10.2.1
Clock synchronization and hardware processing between the network data and the time stamp capture
hardware causes the time stamp point to be slightly delayed. The host software can account for this
delay, as it is fairly deterministic.
mode of operation. Refer to
Once the packet type is matched, according to
verified, the following occurs:
Note: Packets that do not contain an integral number of octets are not considered valid and do not
Capture Locking
The corresponding ports’ clock capture, sequence ID, and source UUID registers can be optionally
locked when a capture event occurs, preventing them from being overwritten until the host clears the
corresponding interrupt flag in the
This is accomplished by setting the corresponding lock enable bit(s) in the
(1588_CONFIG). Each port has two lock enable control bits within this register, which allow the receive
and transmit portions of each port to be locked independently. In addition, a lock enable bit is provided
for each time stamp enabled GPIO (LOCK_ENABLE_GPIO_8 and LOCK_ENABLE_GPIO_9) which
prevents the corresponding GPIO clock capture registers from being overwritten when the GPIO
interrupt in
13.1.4.22, "1588 Configuration Register (1588_CONFIG)," on page 185
the capture locking related bits.
MODE OF OPERATION
The time stamp is loaded into the corresponding ports’ capture registers:
The Sequence ID and Source UUID are loaded into the corresponding ports’ registers:
The corresponding maskable interrupt flag is set in the
(1588_INT_STS_EN). (Refer to
on IEEE 1588 interrupts.)
–On Reception:
–On Transmission:
–On Reception:
–On Transmission:
(1588_CLOCK_HI_RX_CAPTURE_x)
Register (1588_CLOCK_LO_RX_CAPTURE_x)
(1588_CLOCK_HI_TX_CAPTURE_x)
Register (1588_CLOCK_LO_TX_CAPTURE_x)
(1588_SEQ_ID_SRC_UUID_HI_RX_CAPTURE_x)
DWORD Receive Capture Register (1588_SRC_UUID_LO_RX_CAPTURE_x)
Register (1588_SEQ_ID_SRC_UUID_HI_TX_CAPTURE_x)
Low-DWORD Transmit Capture Register (1588_SRC_UUID_LO_TX_CAPTURE_x)
cause a capture.
100 Mbps
10 Mbps
1588 Interrupt Status and Enable Register (1588_INT_STS_EN)
Port x 1588 Clock High-DWORD Receive Capture Register
Port x 1588 Sequence ID, Source UUID High-WORD Receive Capture Register
Port x 1588 Clock High-DWORD Transmit Capture Register
Port x 1588 Sequence ID, Source UUID High-WORD Transmit Capture
Table 10.2 Time Stamp Capture Delay
Chapter 7, "Ethernet PHYs," on page 84
Table 10.2
1588 Interrupt Status and Enable Register
DATASHEET
Section 10.6, "IEEE 1588 Interrupts," on page 140
137
details the time stamp capture delay as a function of the
and
and
Table
Port x 1588 Clock Low-DWORD Transmit Capture
Port x 1588 Clock Low-DWORD Receive Capture
10.1, and the Frame Check Sequence (FCS) is
and
1588 Interrupt Status and Enable Register
Port x 1588 Source UUID Low-
DELAY (+/- 10 nS)
and
120 nS
30 nS
for details on these modes.
Port x 1588 Source UUID
for additional information on
1588 Configuration Register
(1588_INT_STS_EN).
is set. Refer to
Revision 1.7 (06-29-10)
for information
Section