XC5VSX50T-1FFG665I Xilinx Inc, XC5VSX50T-1FFG665I Datasheet - Page 124
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XC5VSX50T-1FFG665I
Manufacturer Part Number
XC5VSX50T-1FFG665I
Description
FPGA Virtex®-5 Family 52224 Cells 65nm (CMOS) Technology 1V 665-Pin FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 SXTr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VSX50T-1FFG665I
Package
665FCBGA
Family Name
Virtex®-5
Device Logic Units
52224
Typical Operating Supply Voltage
1 V
Maximum Number Of User I/os
360
Ram Bits
4866048
Number Of Logic Elements/cells
52224
Number Of Labs/clbs
4080
Total Ram Bits
4866048
Number Of I /o
360
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
665-BBGA, FCBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
HW-V5-ML506-UNI-G - EVALUATION PLATFORM VIRTEX-5
Number Of Gates
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Chapter 4: Block RAM
124
Figure 4-9
(RAMB36).
X-Ref Target - Figure 4-9
Table 4-5: Virtex-5 FPGA Block RAM, FIFO, Simple Dual Port, and ECC Primitives
Notes:
1. All eight primitives are described in the software Libraries guide as well as the language templates.
RAMB36
RAMB36SDP
FIFO36
FIFO36_72
RAMB18
RAMB18SDP
FIFO18
FIFO18_36
Primitive
illustrates all the I/O ports of the 36 Kb true dual-port block RAM primitive
Table 4-5
Supports port widths of x1, x2, x4, x9, x18, x36
Simple dual port (port width x72) and 64-bit ECC primitive (see
Figure
Supports port widths of x4, x9, x18, x36
FIFO (port width x72), optional ECC support
Supports port widths of x1, x2, x4, x9, x18
Simple dual port (port width x36)
Supports port widths of x4, x9, x18
FIFO (port width x36)
Figure 4-9: Block RAM Port Signals (RAMB36)
lists these primitives.
CASCADEOUTREGA
CASCADEOUTLATA
32
16
32
16
CASCADEINREGA
www.xilinx.com
4
4
4
4
4-29)
CASCADEINLATA
DIA
DIPA
ADDRA
WEA
ENA
REGCEA
SSRA
DIB
DIPB
ADDRB
WEB
ENB
REGCEB
SSRB
CLKA
CLKB
CASCADEINLATB
CASCADEINREGB
Description
CASCADEOUTLATB
CASCADEOUTREGB
DOPA
DOPB
DOA
DOB
ug0190_4_10_100906
32
32
4
4
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
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