XC5VSX50T-1FFG665I Xilinx Inc, XC5VSX50T-1FFG665I Datasheet - Page 42

• Manufacturer Part Number: XC5VSX50T-1FFG665I
• Description: FPGA Virtex®-5 Family 52224 Cells 65nm (CMOS) Technology 1V 665-Pin FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 SXTr

Specifications of XC5VSX50T-1FFG665I

• Package: 665FCBGA
• Family Name: Virtex®-5
• Device Logic Units: 52224
• Typical Operating Supply Voltage: 1 V
• Maximum Number Of User I/os: 360
• Ram Bits: 4866048
• Number Of Logic Elements/cells: 52224
• Number Of Labs/clbs: 4080
• Total Ram Bits: 4866048
• Number Of I /o: 360
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 665-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V5-ML506-UNI-G - EVALUATION PLATFORM VIRTEX-5
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 1: Clock Resources
42
Regional Clock Buffer - BUFR
X-Ref Target - Figure 1-19
The regional clock buffer (BUFR) is another clock buffer available in Virtex-5 devices.
BUFRs drive clock signals to a dedicated clock net within a clock region, independent from
Clock Capable I/O
Clock Capable I/O
Clock Capable I/O
Clock Capable I/O
Not all available BUFIOs are shown.
Figure 1-19: BUFIO Driving I/O Logic In a Single Clock Region
P
P
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N
www.xilinx.com
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
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I/O
I/O
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BUFIO
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BUFR
BUFR
To Adjacent
Region
To Adjacent
Region
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
ug190_1_19_060706
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