XC5VSX50T-1FFG665I Xilinx Inc, XC5VSX50T-1FFG665I Datasheet - Page 310

• Manufacturer Part Number: XC5VSX50T-1FFG665I
• Description: FPGA Virtex®-5 Family 52224 Cells 65nm (CMOS) Technology 1V 665-Pin FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 SXTr

Specifications of XC5VSX50T-1FFG665I

• Package: 665FCBGA
• Family Name: Virtex®-5
• Device Logic Units: 52224
• Typical Operating Supply Voltage: 1 V
• Maximum Number Of User I/os: 360
• Ram Bits: 4866048
• Number Of Logic Elements/cells: 52224
• Number Of Labs/clbs: 4080
• Total Ram Bits: 4866048
• Number Of I /o: 360
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 665-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V5-ML506-UNI-G - EVALUATION PLATFORM VIRTEX-5
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 6: SelectIO Resources
310
Table 6-40: Maximum Number of Simultaneously Switching Outputs per Bank (Continued)
Voltage
2.5V
LVCMOS25_2_slow
LVCMOS25_4_slow
LVCMOS25_6_slow
LVCMOS25_8_slow
LVCMOS25_12_slow
LVCMOS25_16_slow
LVCMOS25_24_slow
LVCMOS25_2_fast
LVCMOS25_4_fast
LVCMOS25_6_fast
LVCMOS25_8_fast
LVCMOS25_12_fast
LVCMOS25_16_fast
LVCMOS25_24_fast
LVDCI_25 50 Ω
SSTL2_I
SSTL2_I_DCI
SSTL2_II
SSTL2_II_DCI
HSLVDCI_25 50 Ω
DIFF_SSTL_I
DIFF_SSTL_I_DCI
DIFF_SSTL_II
DIFF_SSTL_II_DCI
LVPECL_25
BLVDS_25
LVDS_25
LVDSEXT_25
RSDS_25
HT_25
IOSTANDARD
www.xilinx.com
Limit per 20-pin Bank
20
20
20
20
20
20
20
20
20
20
20
20
20
15
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
Limit per 40-pin Bank
40
40
40
40
40
40
40
40
40
40
40
40
40
30
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40