XC5VSX50T-1FFG665I Xilinx Inc, XC5VSX50T-1FFG665I Datasheet - Page 196

• Manufacturer Part Number: XC5VSX50T-1FFG665I
• Description: FPGA Virtex®-5 Family 52224 Cells 65nm (CMOS) Technology 1V 665-Pin FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 SXTr

Specifications of XC5VSX50T-1FFG665I

• Package: 665FCBGA
• Family Name: Virtex®-5
• Device Logic Units: 52224
• Typical Operating Supply Voltage: 1 V
• Maximum Number Of User I/os: 360
• Ram Bits: 4866048
• Number Of Logic Elements/cells: 52224
• Number Of Labs/clbs: 4080
• Total Ram Bits: 4866048
• Number Of I /o: 360
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 665-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V5-ML506-UNI-G - EVALUATION PLATFORM VIRTEX-5
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 5: Configurable Logic Blocks (CLBs)
196
Designing Large Multiplexers
4:1 Multiplexer
Each LUT can be configured into a 4:1 MUX. The 4:1 MUX can be implemented with a flip-
flop in the same slice. Up to four 4:1 MUXes can be implemented in a slice, as shown in
Figure
X-Ref Target - Figure 5-21
SEL D [1:0], DATA D [3:0]
SEL C [1:0], DATA C [3:0]
SEL B [1:0], DATA B [3:0]
SEL A [1:0], DATA A [3:0]
5-21.
Input
Input
Input
Input
CLK
Figure 5-21: Four 4:1 Multiplexers in a Slice
www.xilinx.com
(D[6:1])
(C[6:1])
(B[6:1])
(A[6:1])
(CLK)
6
6
6
6
A[6:1]
A[6:1]
A[6:1]
A[6:1]
LUT
LUT
LUT
LUT
SLICE
O6
O6
O6
O6
(Optional)
(Optional)
(Optional)
(Optional)
D Q
D Q
D Q
D Q
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
(DQ)
(CQ)
(BQ)
(AQ)
(D)
(C)
(B)
(A)
4:1 MUX Output
Registered
Output
4:1 MUX Output
Registered
Output
4:1 MUX Output
Registered
Output
4:1 MUX Output
Registered
Output
UG190_5_21_050506