XC5VSX50T-1FFG665I Xilinx Inc, XC5VSX50T-1FFG665I Datasheet - Page 360

• Manufacturer Part Number: XC5VSX50T-1FFG665I
• Description: FPGA Virtex®-5 Family 52224 Cells 65nm (CMOS) Technology 1V 665-Pin FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 SXTr

Specifications of XC5VSX50T-1FFG665I

• Package: 665FCBGA
• Family Name: Virtex®-5
• Device Logic Units: 52224
• Typical Operating Supply Voltage: 1 V
• Maximum Number Of User I/os: 360
• Ram Bits: 4866048
• Number Of Logic Elements/cells: 52224
• Number Of Labs/clbs: 4080
• Total Ram Bits: 4866048
• Number Of I /o: 360
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 665-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V5-ML506-UNI-G - EVALUATION PLATFORM VIRTEX-5
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 8: Advanced SelectIO Logic Resources
360
ISERDES_NODELAY Clocking Methods
NUM_CE Attribute
SERDES_MODE Attribute
Networking Interface Type
X-Ref Target - Figure 8-5
The NUM_CE attribute defines the number of clock enables (CE1 and CE2) used. The
possible values are 1 and 2 (default = 2).
The SERDES_MODE attribute defines whether the ISERDES_NODELAY module is a
master or slave when using width expansion. The possible values are MASTER and
SLAVE. The default value is MASTER. See
The phase relationship of CLK and CLKDIV is important in the serial-to-parallel
conversion process. CLK and CLKDIV are (ideally) phase-aligned within a tolerance.
There are several clocking arrangements within the FPGA to help the design meet the
phase relationship requirements of CLK and CLKDIV. The only valid clocking
arrangements for the ISERDES_NODELAY block using the networking interface type are:
•
•
•
Figure 8-5: Internal Connections of ISERDES_NODELAY When in Memory Mode
CLK driven by BUFIO, CLKDIV driven by BUFR
CLK driven by DCM, CLKDIV driven by the CLKDV output of the same DCM
CLK driven by PLL, CLKDIV driven by CLKOUT[0:5] of same PLL
CLKDIV
OCLK
CLK
D
ICE
ICE
FF0
FF1
www.xilinx.com
ICE
ICE
ISERDES Width
FF2
FF3
FF4
FF5
Expansion.
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
FF6
FF7
FF8
FF9
ug190_8_05_100307
Q1
Q2
Q3
Q4