XC5VSX50T-1FFG665I Xilinx Inc, XC5VSX50T-1FFG665I Datasheet - Page 83

• Manufacturer Part Number: XC5VSX50T-1FFG665I
• Description: FPGA Virtex®-5 Family 52224 Cells 65nm (CMOS) Technology 1V 665-Pin FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 SXTr

Specifications of XC5VSX50T-1FFG665I

• Package: 665FCBGA
• Family Name: Virtex®-5
• Device Logic Units: 52224
• Typical Operating Supply Voltage: 1 V
• Maximum Number Of User I/os: 360
• Ram Bits: 4866048
• Number Of Logic Elements/cells: 52224
• Number Of Labs/clbs: 4080
• Total Ram Bits: 4866048
• Number Of I /o: 360
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 665-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V5-ML506-UNI-G - EVALUATION PLATFORM VIRTEX-5
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

VHDL and Verilog Templates, and the Clocking Wizard
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
X-Ref Target - Figure 2-16
VHDL and Verilog instantiation templates are available in the Libraries Guide for all
primitives. In addition, VHDL and Verilog files are generated by the Clocking Wizard in
the ISE software. The Clocking Wizard sets appropriate DCM attributes, input/output
clocks, and buffers for general use cases.
IBUFG
IBUFG
Figure 2-16: Two DCMs Driving a PLL
www.xilinx.com
VHDL and Verilog Templates, and the Clocking Wizard
CLKIN1
CLKIN2
CLKFBIN
RST
CLKIN
CLKFBIN
CLKIN
CLKFBIN
RST
DCM1
DCM
PLL
CLKFBOUT
CLKFX180
CLKFX180
CLK2X180
CLK2X180
CLKOUT0
CLKOUT1
CLKOUT2
CLKOUT3
CLKOUT4
CLKOUT5
CLK180
CLK270
CLK180
CLK270
CLKDV
CLKDV
CLKFX
CLKFX
CLK2X
CLK2X
CLK90
CLK90
CLK0
CLK0
BUFG
BUFG
BUFG
BUFG
BUFG
ug190_2_18_040906
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