MAX11008BETM+ Maxim Integrated Products, MAX11008BETM+ Datasheet - Page 26

• Manufacturer Part Number: MAX11008BETM+
• Description: RF Wireless Misc IC CTLR LDMOS BIAS DUAL
• Manufacturer: Maxim Integrated Products

Specifications of MAX11008BETM+

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

complete the ADC powers down, BUSY is pulled low,
and the results for all of the selected channels are
available in the FIFO.
The duration of the BUSY pulse is additive, depending
on the channel conversion sequence selected. The
BUSY pulse is set typically for 72µs by temperature
conversions; 52µs by PGAOUT conversions, and 7µs
by ADCIN conversions.
In clock mode 01, power-up, acquisition, conversion,
and power-down are all initiated through a single pulse
on CNVST and performed automatically using the inter-
nal oscillator. Initiate a scan by writing to the ADC con-
version register and setting CNVST low for at least
20ns. The ADC sets the BUSY output high, powers up,
and scans all requested channels storing the results in
the FIFO if the ADCMON bit has been set. After the
scan is complete, the ADC powers down, BUSY is
pulled low, and the results for all of the selected chan-
nels are available in the FIFO. The BUSY pulse behav-
ior is identical to that of clock mode 00.
Dual RF LDMOS Bias Controller with
Nonvolatile Memory
Figure 15. ADC Clock Mode 11 Example
26
______________________________________________________________________________________
OPERATIONS
INTERNAL
CONVERT REGISTER TO
CNVST
BUSY
SET UP ADC SCAN
WRITE TO ADC
ADCMON = 1
FBGON = 1,
t
CNV
= 20ns (typ)
INTERNAL TEMPERATURE READING, PGA1 OUTPUT, AND ADCIN1 CONVERSION TIMING IN CLOCK MODE 11
TEMPERATURE
CONVERSION
70µs (typ)
CONVERSION RESULT
AVAILABLE IN FIFO
Clock Mode 01
TEMPERATURE
IDLE MODE,
POWERED
REF AND
SENSOR
TEMP
t
ACQ
ACQUISITION
PGA 1
= 30µs (typ)
Clock mode 10 is reserved. Do not use this clock
mode.
In clock mode 11, set the FBGON bit. Conversions are
initiated one at a time through CNVST and performed
using the internal oscillator. In this mode, the acquisition
time is controlled by the time CNVST is low. CNVST is
resynchronized by the internal oscillator, resulting in a
one-clock cycle (typically 320ns) uncertainty in the exact
sampling instant. Different timing parameters apply
depending if the conversion is temperature, from ADCIN,
or from PGAOUT (as specified in the Clock Mode 00
section). Figure 15 shows a conversion time example.
Both internal and external temperature conversions are
internally timed. Pull CNVST low for a minimum of 20ns
(t
output goes high and the temperature conversion result
is available in the FIFO (if the ADCMON bit is set) 72µs
(typ) after BUSY goes low again.
CNV11
CONVERSION
) to trigger a temperature conversion. The BUSY
22µs (typ)
PGA 1
RESULT AVAILABLE
PGA 1 OUTPUT
CONVERSION
IN FIFO
Acquisitions and Conversions
IDLE MODE,
POWERED
REF AND
SENSOR
TEMP
t
ACQ
= 1.5µs (typ)
RESULT AVAILABLE
CONVERSION
Externally Timed
ADCIN 1
IN FIFO
END OF
Clock Mode 10
Clock Mode 11
SCAN