MAX11008BETM+ Maxim Integrated Products, MAX11008BETM+ Datasheet - Page 64

• Manufacturer Part Number: MAX11008BETM+
• Description: RF Wireless Misc IC CTLR LDMOS BIAS DUAL
• Manufacturer: Maxim Integrated Products

Specifications of MAX11008BETM+

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Dual RF LDMOS Bias Controller with
Nonvolatile Memory
Table 24a. FIFO Read Channel Tags (TAG[3:0])
Table 25. Software Clear Register
X = Don’t care.
NA = Not applicable.
64
TAG3
DATA BITS
0
0
0
0
0
0
0
1
1
1
1
1
1
______________________________________________________________________________________
D[15:7]
D6
D5
D4
D3
D2
D1
D0
CHANNEL TAGS
TAG2
0
0
0
0
1
1
1
0
0
0
0
1
1
TAG1
0
0
1
1
0
0
1
0
0
1
1
1
1
BIT NAME
ALMSCLR
DAC2RST
DAC1RST
FULLRST
FIFOCLR
ARMRST
AVGCLR
Unused
TAG0
0
1
0
1
0
1
0
0
1
0
1
0
1
Internal temperature sensor measurement. ADCMON bit must be set.
Channel 1 external temperature measurement. ADCMON bit must be set.
Channel 1 drain current measurement. ADCMON bit must be set.
ADCIN1 input measurement. ADCMON bit must be set.
Channel 2 external temperature measurement. ADCMON bit must be set.
Channel 2 drain current measurement. ADCMON bit must be set.
ADCIN2 input measurement. ADCMON bit must be set.
Channel 1 temperature average. AVGMON bit must be set.
Channel 1 APC average. AVGMON bit must be set.
Channel 2 temperature average. AVGMON bit must be set.
Channel 2 APC average. AVGMON bit must be set.
Error tag. Indicates data may be corrupted.
Empty FIFO tag. This tag appears during a FIFO read if the FIFO is empty at the time the read
command is made. In addition to this channel tag, the current value of the Flag register is
provided in place of the ADC data.
RESET STATE
NA
NA
NA
NA
NA
NA
X
0
Unused bits.
Full reset bit. If ARMRST has been set to 1 in a previous write operation, set
FULLRST to 1 to perform a full reset. Otherwise, a full reset will not be
performed and the value of FULLRST remains unchanged.
Full reset enable bit. Set to 1 at the same time FULLRST is set to 0 to
enable full reset capabilities.
Alarm threshold registers reset bit. Set to 1 to clear all alarm threshold
registers and their respective flags in the Flag register.
Average clear enable bit. Set the AVGCLR bit to 1 to clear the average and
hysteresis memory for all lookup operations.
FIFO clear bit. Set to 1 to clear the FIFO.
DAC 2 reset bit. Set to 1 to clear DAC2 input and output registers.
DAC 1 reset bit. Set to 1 to clear DAC1 input and output registers.
ADC DATA DESCRIPTION
FUNCTION