MAX11008BETM+ Maxim Integrated Products, MAX11008BETM+ Datasheet - Page 40

• Manufacturer Part Number: MAX11008BETM+
• Description: RF Wireless Misc IC CTLR LDMOS BIAS DUAL
• Manufacturer: Maxim Integrated Products

Specifications of MAX11008BETM+

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Dual RF LDMOS Bias Controller with
Nonvolatile Memory
The MAX11008 features 4Kb of EEPROM capable of
storing up to 256 16-bit data words. The first 64 data
words of the EEPROM contain configuration data (see
Table 4) while the remaining 192 data words are pro-
grammable and used for storing temperature and APC
LUTs. The MAX11008 utilizes the LUT values to perform
gate voltage calculations (see the V
Equation section). See the First-In-First-Out (FIFO) , LUT
Streaming Mode , and Message Mode sections for more
information on how to program and read from the
EEPROM. See the Temperature/APC LUT Configuration
Registers section for information on how to configure
the LUTs and how values are retrieved from the LUTs
for V
Upon power-on reset, the data contained within specif-
ic EEPROM locations is copied directly to correspond-
ing locations within the register address map
depending on the state of the magic number (see the
Magic Number section).
• Locations 0x10–0x1F are directly copied to their cor-
• Locations 0x2C–0x33 are conditionally copied to
Table 4a. EEPROM Address Bit Map
40
HEX
1A
1B
1C
1D
1D
1E
2C
2D
2E
3C
3D
3E
10
11
12
13
14
15
16
17
18
19
1F
1F
2F
30
31
32
33
37
3F
responding locations within the register address
map.
their corresponding locations within the register
address map. Set the MSB (labeled WCTRAM) to 1
for locations 0x2C–0x33 to be copied to the register
address map (see Table 4a).
MAGIC NUMBER
GATE_
______________________________________________________________________________________
EE_ADCCON
EE_ALMHCF
MNEMONIC
EE_ALMSCF
EE_HIST_AP
EE_HIST_AP
EE_HIST_AP
EE_HIST_AP
EE_PGACAL
EE_IODAC1
EE_IODAC2
EE_SSHUT
EE_HCFIG
EE_SCFIG
EE_VSET1
EE_VSET2
EE_IDAC1
EE_IDAC2
EE_TLUT1
EE_ALUT1
EE_TLUT2
EE_ALUT2
EE_LDAC
EE_TH1
EE_TH2
EE_TL1
EE_IH1
EE_TL2
EE_IH2
EE_IL1
EE_IL2
calculations. See Table 5.
TABLE
16b
16b
16a
16a
10
10
11
12
13
14
15
15
17
18
17
18
19
20
21
22
—
5
5
5
5
7
8
9
7
8
9
T1AVGCTL
T2AVGCTL
WCTRAM
WCTRAM
WCTRAM
WCTRAM
WCTRAM
WCTRAM
WCTRAM
WCTRAM
T1HIST3
T1HIST3
T1HIST3
T2HIST3
BIT 15
POFF5
POFF5
POFF5
POFF5
X
X
X
X
X
X
X
X
X
X
X
X
1
Nonvolatile Initialization Values
T1LIMIT2
T2LIMIT2
T1HIST2
T1HIST2
T1HIST2
T2HIST2
BIT 14
POFF4
POFF4
POFF4
POFF4
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
T1LIMIT1
T2LIMIT1
T1HIST1
T1HIST1
T1HIST1
T2HIST2
POFF3
POFF3
POFF3
POFF3
BIT 13
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
T1LIMIT0
T1LIMIT0
T1HIST0
T1HIST0
T1HIST0
T2HIST0
BIT 12
POFF2
POFF2
POFF2
POFF2
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
GATE
FIFOSTAT
A2AVG
LDAC2
BIT 11
POFF1
POFF1
POFF1
POFF1
D11
D11
D11
D11
D11
D11
D11
D11
D11
D11
D11
D11
D11
D11
D11
D11
X
X
X
X
X
X
X
1
EEPROM
_ Output
ADCMON
AVGMON
TCOMP2
T2AVG
BIT 10
POFF0
POFF0
POFF0
POFF0
D10
D10
D10
D10
D10
D10
D10
D10
D10
D10
D10
D10
D10
D10
D10
D10
X
X
X
X
X
X
0
APCCOMP2
PG2SET1
INTEMP2
A1AVG
BIT 9
INT1
INT1
INT1
INT1
D9
D9
D9
D9
D9
D9
D9
D9
D9
D9
D9
D9
D9
D9
D9
D9
X
X
X
X
X
X
1
PG2SET0
ALMCMP
T1AVG
TSRC2
BIT 8
INT0
INT0
INT0
INT0
By correctly configuring the initialization values stored
within the EEPROM, the MAX11008 can automatically
enter V
a host processor. This autonomous operation is useful
in some application areas where a host controller is not
desired.
Changes made to the working registers during opera-
tion are volatile. To change a register’s nonvolatile ini-
tialization value, the corresponding EEPROM location
must be written by the LUT streaming protocol.
The address location 0x37 of the EEPROM is referred
to as the magic address. If the magic address is pro-
grammed with the magic number (0xAA55), the values
stored in address locations 0x10–0x1F and 0x2C–0x33
are loaded into the working registers ( see the Register
Address Map section) during power-up initialization.
Address locations 0x10–0x1F are unconditionally
loaded into the working registers, whereas address
locations 0x2C–0x33 are only loaded if bit D15
(WCTRAM) of the address is set to 1. If magic address
location 0x37 is not programmed with the magic num-
ber (0xAA55), the EEPROM is determined to be unpro-
grammed; the power-up initialization load is then
bypassed and the working registers default to their
power-on reset value.
The values stored within the LUT section of the
EEPROM are 16-bit signed (two’s complement)
D8
D8
D8
D8
D8
D8
D8
D8
D8
D8
D8
D8
D8
D8
D8
D8
X
X
X
X
X
X
0
APCSRC21
ALMHYST1
A1AVGCTL
A2AVGCTL
CONCONV
TALARM2
PG1SET1
PSIZE1
PSIZE1
PSIZE1
PSIZE1
BIT 7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
X
X
X
0
GATE_
APCSRC20
ALMHYST0
PG1SET1
A1LIMIT2
A2LIMIT2
ADCIN2
PSIZE0
PSIZE0
PSIZE0
PSIZE0
TWIN2
BIT 6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
X
X
X
1
compensation mode without the need for
ALMCLMP21
IALARM2
A1LIMIT1
A2LIMIT1
CKSEL1
LDAC1
TSIZE2
TSIZE2
TSIZE2
TSIZE2
BIT 5
CS2
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
X
X
X
0
ALMCLMP20
EXTTEMP2
A1LIMIT0
A2LIMIT0
TCOMP1
CKSEL0
TSIZE1
TSIZE1
TSIZE1
TSIZE1
IWIN2
BIT 4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
X
X
X
1
ALMCLMP11
APCCOMP1
ADCREF1
TALARM1
A1HIST3
A2HIST3
ADCIN1
FBGON
TSIZE0
TSIZE0
TSIZE0
TSIZE0
BIT 3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
X
X
0
ALMCLMP10
ADCREF0
A1HIST2
A2HIST2
TRACK
OSCPD
TWIN1
TSRC1
BIT 2
SOT2
SOT2
SOT2
SOT2
CS1
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
X
1
Magic Number
LUT Values
APCSRC11
DAC_CH2
DACREF1
EXTEMP1
IALARM1
ALMPOL
DAC2PD
A1HIST1
A2HIST1
DOCAL
BIT 1
SOT1
SOT1
SOT1
SOT1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
0
APCSRC10
SELFTIME
DAC_CH1
DACREF0
ALMOPN
DAC1PD
A1HIST0
A2HIST0
INTEMP
IWIN1
BIT 0
SOT0
SOT0
SOT0
SOT0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
1