723624L12PF Integrated Device Technology (Idt), 723624L12PF Datasheet - Page 17

• Manufacturer Part Number: 723624L12PF
• Description: FIFO Mem Sync Dual Bi-Dir 256 x 36 x 2 128-Pin TQFP
• Manufacturer: Integrated Device Technology (Idt)

Specifications of 723624L12PF

• Package: 128TQFP
• Configuration: Dual
• Bus Directional: Bi-Directional
• Density: 18 Kb
• Organization: 256x36x2
• Data Bus Width: 36 Bit
• Timing Type: Synchronous
• Typical Operating Supply Voltage: 5 V
• Operating Temperature: 0 to 70 °C

NOTES:
1. Partial Reset is performed in the same manner for FIFO2.
2. MRS1 must be HIGH during Partial Reset.
3. If BE/FWFT is HIGH, then EFB/ORB will go LOW one CLKB cycle earlier than in this case where BE/FWFT is LOW.
EFB/ORB
NOTES:
1. FIFO2 (MRS2) Master Reset is performed in the same manner to load X2 and Y2 with a preset value. For FIFO2 Master Reset (MRS1) must toggle simultaneously with MRS2.
2. PRS1 must be HIGH during Master Reset.
3. If BE/FWFT is HIGH, then EFB/ORB will go LOW one CLKB cycle earlier than the case where BE/FWFT is LOW.
IDT723624/723634/723644 CMOS SyncBiFIFO™ WITH BUS-MATCHING
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
EFB/ORB
BE/FWFT
FS1,FS0
FFA/IRA
FFA/IRA
MRS1
CLKA
CLKB
MBF1
CLKA
CLKB
MBF1
PRS1
SPM
AFA
AEB
AEB
AFA
Figure 3. FIFO1 Master Reset and Loading X1 and Y1 with a Preset Value of Eight
t
t
RSTS
RSTS
t
t
t
RSF
RSF
t
t
RSF
t
RSF
RSF
RSF
Figure 4. FIFO1 Partial Reset
t
WFF
t
WFF
(1)
17
(IDT Standard and FWFT Modes)
t
SPMS
t
FSS
t
t
t
REF
BES
REF (3)
(3)
0,1
BE
t
RSTH
t
RSTH
t
BEH
t
(1)
t
FSH
SPMH
(IDT Standard and FWFT Modes)
COMMERCIAL TEMPERATURE RANGE
t
FWS
FWFT
t
t
WFF
WFF
3270 drw06
3270 drw05