723624L12PF Integrated Device Technology (Idt), 723624L12PF Datasheet - Page 29

• Manufacturer Part Number: 723624L12PF
• Description: FIFO Mem Sync Dual Bi-Dir 256 x 36 x 2 128-Pin TQFP
• Manufacturer: Integrated Device Technology (Idt)

Specifications of 723624L12PF

• Package: 128TQFP
• Configuration: Dual
• Bus Directional: Bi-Directional
• Density: 18 Kb
• Organization: 256x36x2
• Data Bus Width: 36 Bit
• Timing Type: Synchronous
• Typical Operating Supply Voltage: 5 V
• Operating Temperature: 0 to 70 °C

A0-A35
B0-B35
NOTES:
1. t
2. If Port B size is word or byte, IRB is set LOW by the last word or byte write of the long word, respectively.
IDT723624/723634/723644 CMOS SyncBiFIFO™ WITH BUS-MATCHING
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
CLKA
CLKB
W/RB
W/RA
MBA
ORA
MBB
CSA
ENA
CSB
ENB
CLKB edge is less than t
IRB
SKEW1
is the minimum time between a rising CLKA edge and a rising CLKB edge for IRB to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge and rising
FIFO2 FULL
LOW
LOW
LOW
LOW
HIGH
LOW
Previous Word in FIFO2 Output Register
t
CLKH
SKEW1
t
CLK
, then IRB may transition HIGH one CLKB cycle later than shown.
t
Figure 21. IRB Flag Timing and First Available Write when FIFO2 is Full (FWFT Mode)
ENS2
t
CLKL
t
t
SKEW1
ENH
t
A
(1)
1
t
CLKH
t
CLK
29
t
CLKL
2
Next Word From FIFO2
t
WFF
t
t
ENS2
ENS2
t
DS
COMMERCIAL TEMPERATURE RANGE
To FIFO2
Write
t
t
WFF
DH
t
t
ENH
ENH
3270 drw23