723624L12PF Integrated Device Technology (Idt), 723624L12PF Datasheet - Page 26

• Manufacturer Part Number: 723624L12PF
• Description: FIFO Mem Sync Dual Bi-Dir 256 x 36 x 2 128-Pin TQFP
• Manufacturer: Integrated Device Technology (Idt)

Specifications of 723624L12PF

• Package: 128TQFP
• Configuration: Dual
• Bus Directional: Bi-Directional
• Density: 18 Kb
• Organization: 256x36x2
• Data Bus Width: 36 Bit
• Timing Type: Synchronous
• Typical Operating Supply Voltage: 5 V
• Operating Temperature: 0 to 70 °C

NOTES:
1. t
2. If Port B size is word or byte, t
B0-B35
A0-A35
IDT723624/723634/723644 CMOS SyncBiFIFO™ WITH BUS-MATCHING
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
CLKA
W/RA
W/RB
CLKB
and rising CLKA edge is less than t
MBB
SKEW1
MBA
CSB
ENB
CSA
ENA
EFA
FFB
is the minimum time between a rising CLKB edge and a rising CLKA edge for EFA to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge
LOW
HIGH
FIFO2 Empty
LOW
LOW
LOW
LOW
t
t
ENS2
ENS2
t
DS
Figure 18. EFA
SKEW1
is referenced to the rising CLKB edge that writes the last word or byte of the long word, respectively.
W1
SKEW1
EFA
EFA
EFA
EFA Flag Timing and First Data Read when FIFO2 is Empty (IDT Standard Mode)
, then the transition of EFA HIGH may occur one CLKA cycle later than shown.
t
SKEW1
t
t
t
ENH
ENH
DH
(1)
t
CLKH
1
t
CLK
t
CLKL
26
t
2
REF
t
CLKH
t
ENS2
t
CLK
t
CLKL
t
REF
t
A
t
ENH
COMMERCIAL TEMPERATURE RANGE
W1
3270 drw20