723624L12PF Integrated Device Technology (Idt), 723624L12PF Datasheet - Page 27

• Manufacturer Part Number: 723624L12PF
• Description: FIFO Mem Sync Dual Bi-Dir 256 x 36 x 2 128-Pin TQFP
• Manufacturer: Integrated Device Technology (Idt)

Specifications of 723624L12PF

• Package: 128TQFP
• Configuration: Dual
• Bus Directional: Bi-Directional
• Density: 18 Kb
• Organization: 256x36x2
• Data Bus Width: 36 Bit
• Timing Type: Synchronous
• Typical Operating Supply Voltage: 5 V
• Operating Temperature: 0 to 70 °C

NOTES:
1. t
2. If Port B size is word or byte, t
IDT723624/723634/723644 CMOS SyncBiFIFO™ WITH BUS-MATCHING
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
B0-B35
A0-A35
W/RB
CLKB
CLKA
W/RA
CLKA edge is less than t
SKEW1
MBA
MBB
ORB
CSB
ENB
ENA
CSA
IRA
is the minimum time between a rising CLKB edge and a rising CLKA edge for IRA to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge and rising
FIFO1 Full
LOW
LOW
LOW
HIGH
HIGH
HIGH
Previous Word in FIFO1 Output Register
t
CLKH
SKEW1
t
CLK
SKEW1
t
, then IRA may transition HIGH one CLKA cycle later than shown.
Figure 19. IRA Flag Timing and First Available Write when FIFO1 is Full (FWFT Mode)
ENS2
t
CLKL
is referenced to the rising CLKB edge that reads the last word or byte write of the long word, respectively.
t
t
SKEW1
ENH
t
A
(1)
1
t
CLKH
t
CLK
27
t
CLKL
2
Next Word From FIFO1
t
WFF
t
t
ENS2
ENS2
t
DS
To FIFO1
Write
COMMERCIAL TEMPERATURE RANGE
t
t
t
t
ENH
WFF
DH
ENH
3270 drw21