723624L12PF Integrated Device Technology (Idt), 723624L12PF Datasheet - Page 23

• Manufacturer Part Number: 723624L12PF
• Description: FIFO Mem Sync Dual Bi-Dir 256 x 36 x 2 128-Pin TQFP
• Manufacturer: Integrated Device Technology (Idt)

Specifications of 723624L12PF

• Package: 128TQFP
• Configuration: Dual
• Bus Directional: Bi-Directional
• Density: 18 Kb
• Organization: 256x36x2
• Data Bus Width: 36 Bit
• Timing Type: Synchronous
• Typical Operating Supply Voltage: 5 V
• Operating Temperature: 0 to 70 °C

NOTES:
1. t
2. If Port B size is word or byte, ORB is set LOW by the last word or byte read from FIFO1, respectively.
IDT723624/723634/723644 CMOS SyncBiFIFO™ WITH BUS-MATCHING
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
If the time between the rising CLKA edge and rising CLKB edge is less than t
cycle later than shown.
SKEW1
A0-A35
B0-B35
CLKA
CLKB
W/RB
WRA
MBA
MBB
CSA
ENA
ORB
ENB
CSB
IRA
is the minimum time between a rising CLKA edge and a rising CLKB edge for ORB to transition HIGH and to clock the next word to the FIFO1 output register in three CLKB cycles.
FIFO1 Empty
HIGH
LOW
HIGH
LOW
HIGH
LOW
Figure 15. ORB Flag Timing and First Data Word Fall Through when FIFO1 is Empty (FWFT Mode)
t
t
ENS2
ENS2
t
DS
W1
Old Data in FIFO1 Output Register
t
SKEW1
t
t
ENH
t
ENH
DH
(1)
t
CLKH
1
t
CLK
SKEW1
t
CLKL
, then the transition of ORB HIGH and load of the first word to the output register may occur one CLKB
23
2
t
CLKH
t
CLK
t
CLKL
t
REF
3
t
A
t
ENS2
COMMERCIAL TEMPERATURE RANGE
t
REF
t
ENH
W1
3270 drw17