723624L12PF Integrated Device Technology (Idt), 723624L12PF Datasheet - Page 24

• Manufacturer Part Number: 723624L12PF
• Description: FIFO Mem Sync Dual Bi-Dir 256 x 36 x 2 128-Pin TQFP
• Manufacturer: Integrated Device Technology (Idt)

Specifications of 723624L12PF

• Package: 128TQFP
• Configuration: Dual
• Bus Directional: Bi-Directional
• Density: 18 Kb
• Organization: 256x36x2
• Data Bus Width: 36 Bit
• Timing Type: Synchronous
• Typical Operating Supply Voltage: 5 V
• Operating Temperature: 0 to 70 °C

NOTES:
1. t
2. If Port B size is word or byte, EFB is set LOW by the last word or byte read from FIFO1, respectively.
A0-A35
B0-B35
IDT723624/723634/723644 CMOS SyncBiFIFO™ WITH BUS-MATCHING
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
CLKA
CLKB
W/RB
WRA
and rising CLKB edge is less than t
MBA
MBB
SKEW1
CSA
ENA
CSB
ENB
EFB
FFA
is the minimum time between a rising CLKA edge and a rising CLKB edge for EFB to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge
FIFO1 Empty
HIGH
LOW
LOW
LOW
HIGH
HIGH
Figure 16. EFB
t
t
ENS2
ENS2
t
DS
EFB
EFB
EFB Flag Timing and First Data Read Fall Through when FIFO1 is Empty (IDT Standard Mode)
EFB
SKEW1
W1
, then the transition of EFB HIGH may occur one CLKB cycle later than shown.
t
SKEW1
t
t
t
ENH
ENH
DH
(1)
t
CLKH
1
t
CLK
t
CLKL
24
t
2
REF
t
t
CLKH
ENS2
t
CLK
t
CLKL
t
REF
t
A
t
ENH
COMMERCIAL TEMPERATURE RANGE
W1
3270 drw18