MSC8144ADS Freescale, MSC8144ADS Datasheet - Page 29

• Manufacturer Part Number: MSC8144ADS
• Manufacturer: Freescale

Specifications of MSC8144ADS

• Lead Free Status / RoHS Status: Compliant

Serial RapidIO Ports
5.4 Serial RapidIO Ports
The MSC8144 serial RapidIO port Lane 0 (serial RapidIO 1x) is connected directly to the AMC
edge connector. See Table 6-3 on page 6-11 for a detailed list of these connections. It is possible
to connect the serial RapidIO Lanes 2 and 3 to the AMC edge connector or the SGMII switch
88E6152 ports 2 and 3 when configured as SGMII ports 1and 2, but you must assemble
appropriate serial capacitors for this configuration. Freescale configures the ports using customer
requirements when the board is ordered
5.5 TDM Ports and Peripheral
The TDM ports use a 16-bit voice codec and a T1/E1 interface.
5.5.1 16-bit Voice Codec
The codec is a TI dual TLV320AIC22PT that features two analog-to-digital converter (ADC)
channels and two digital-to-analog converter (DAC) channels that can connect to a handset,
headset, speaker, microphone, or a subscriber line via an analog crosspoint. The codec supports
8-Bit A-Law/μ-Law compounded data or 16-bit linear data complying with G.711. It also
supports 8- and 16-kHz sampling rates, and its filters comply with G.712 and G.722 standards.
2
Programming of the codec is performed via the I
C interface from the Host processor
2
(MPC8560), the MSC8144 or the FPGA I
C controller. Power down signal CODEC_EN from
bit BCSR0[0] isolates the codec drivers from TDM0 bus. The codec is enabled by default.
5.5.2 E1/T1 Framer
The E1/T1 framer is implemented using the Dallas DS26521, a single chip framer and LIU
combination for T1, E1, and J1 applications that supports both long haul and short haul lines.
The transceiver consists of a line interface unit, framer, HDLC controller, elastic store, and a
TDM backplane interface (H.100). The framer is configured via the SPI bus. Access is available
from the SPI port of the MPC8560 as well as via the MSC8144 SPI. The line interface is via a
transformer and dual RJ-45 connector.
The TDM interface to the MSC8144 TDM port is based on a backplane configuration with an
elastic store enable. All clocks are produced from a master clock of 2.048 MHz. The MSC8144
TDM ports 1 and 2 are programmed in Clock/Sync shared mode. Data channels use TDM port 1
lanes 1 and 2. Signaling channels use TDM port 2 lanes 1 and 2. See Table 5-2 on page 5-7 for
the configuration modes of all peripherals regarding TDM. For each framer (TDM Enable and
Reset), there are two sets of control signals: BCSR0[1], BCSR2[4] and BCSR0[2], and
BCSR2[5] that allow isolation of the framer outputs.
MSC8144ADS MSC8144, Rev. 0
Freescale Semiconductor
5-5